Zobrazeno 1 - 10
of 30
pro vyhledávání: '"Guiqiang Dong"'
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24:2654-2664
A multilevel per cell (MLC) technique significantly improves the storage density, but also poses serious data integrity challenge for NAND flash memory. This consequently makes the low-density parity-check (LDPC) code and the soft-decision memory sen
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::05515c1e05167efef598c9592569d968
https://doi.org/10.1109/tvlsi.2016.2535224
https://doi.org/10.1109/tvlsi.2016.2535224
Publikováno v:
Circuits, Systems, and Signal Processing. 34:557-577
Multi-level per cell (MLC) technique has been widely used to improve the storage density of NAND flash memory. In current design practice, bits stored in one cell are mapped to different pages, and all pages are protected with the same error correcti
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::64a80b9c54408e37bb301d2fe8fbef5d
https://doi.org/10.1007/s00034-014-9869-3
https://doi.org/10.1007/s00034-014-9869-3
Publikováno v:
Chinese Science Bulletin. 59:3554-3561
This paper concerns a decoding strategy to improve the throughput in NAND flash memory using low-density parity-check (LDPC) codes. As the reliability of NAND flash memory continues degrading, conventional error correction codes have become increasin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b2b532e2e245c1352b4afcad746e3ed3
https://doi.org/10.1007/s11434-014-0510-4
https://doi.org/10.1007/s11434-014-0510-4
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22:1270-1280
This paper advocates a lifetime-aware progressive programming concept to improve single-level per cell NAND flash memory write endurance. NAND flash memory program/erase (P/E) cycling gradually degrades memory cell storage noise margin, and sufficien
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dbf076339136ab0a4907c91966bd7b23
https://doi.org/10.1109/tvlsi.2013.2267753
https://doi.org/10.1109/tvlsi.2013.2267753
Autor:
Tsung-Yi Chen, Guiqiang Dong, Hari Shankar, Jiadong Wang, Kasra Vakilinia, Richard D. Wesel, Tong Zhang, Thomas A. Courtade
Publikováno v:
IEEE Journal on Selected Areas in Communications. 32:880-891
Multiple reads of the same Flash memory cell with distinct word-line voltages provide enhanced precision for LDPC decoding. In this paper, the word-line voltages are optimized by maximizing the mutual information (MI) of the quantized channel. The en
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a4adf2164f4a7f9ceb8c9ae4255ad78f
https://doi.org/10.1109/jsac.2014.140508
https://doi.org/10.1109/jsac.2014.140508
Enabling NAND Flash Memory Use Soft-Decision Error Correction Codes at Minimal Read Latency Overhead
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 60:2412-2421
With the aggressive technology scaling and use of multi-bit per cell storage, NAND flash memory is subject to continuous degradation of raw storage reliability and demands more and more powerful error correction codes (ECC). This inevitable trend mak
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d1d853238a830e0f0c7d755a66662769
https://doi.org/10.1109/tcsi.2013.2244361
https://doi.org/10.1109/tcsi.2013.2244361
Publikováno v:
IEEE Transactions on Magnetics. 49:4761-4767
With the distinct advantage of retaining conventional head and media, the emerging shingled recording technology improves areal storage density through intentional track overlapping that nevertheless introduces severe intertrack interference (ITI). A
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d5dfcd43f6b9642f5c81470eecf5137e
https://doi.org/10.1109/tmag.2013.2242086
https://doi.org/10.1109/tmag.2013.2242086
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 21:1350-1354
This brief presents a NAND Flash memory wear-leveling algorithm that explicitly uses memory raw bit error rate (BER) as the optimization target. Although NAND Flash memory wear-leveling has been well studied, all the existing algorithms aim to equali
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3ee2e59118ee559287911be6c5b39a94
https://doi.org/10.1109/tvlsi.2012.2210256
https://doi.org/10.1109/tvlsi.2012.2210256
Publikováno v:
IEEE Transactions on Computers. 62:1051-1057
Future flash-based solid-state drives (SSDs) must employ increasingly powerful error correction code (ECC) and digital signal processing (DSP) techniques to compensate the negative impact of technology scaling on NAND flash memory device reliability.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::06d722d6634f615111522d10d6859f1b
https://doi.org/10.1109/tc.2012.54
https://doi.org/10.1109/tc.2012.54
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20:1705-1714
Today and future NAND flash memory will heavily rely on system-level fault-tolerance techniques such as error correction code (ECC) to ensure the overall system storage integrity. Since ECC demands the storage of coding redundancy and hence degrades
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c5a4c2da744947e860a9490f509ff71b
https://doi.org/10.1109/tvlsi.2011.2160747
https://doi.org/10.1109/tvlsi.2011.2160747