Zobrazeno 1 - 10
of 19
pro vyhledávání: '"Guilherme Bontorin"'
Publikováno v:
Electronics, Vol 16, Iss 2, Pp 136-144 (2012)
Hynets, for Hybrid (living-artificial) Networks, are an efficient and adaptable experimental support to explore the dynamics and the adaptation process of biological systems. We present in this paper an innovative platform performing a real-time clos
Externí odkaz:
https://doaj.org/article/8f460bac49f1443db475cfbc62aca958
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 66:2165-2174
A non-linear analytical method is presented for global placement of logic cells in an IC, based on algorithms inspired in Dynamic Systems Theory, also known as Chaotic Systems. The related developed tool is called Chaotic Place. The two-dimensional s
Publikováno v:
LASCAS
It is presented an analytic non-linear method for global placement of cells in circuits based on Dynamic Systems Theory, also known as Chaotic Systems. The related developed tool is called Chaotic Place. The two-dimensional structure of the cells of
Publikováno v:
LASCAS
It is presented a method to reduce the amount of transistors by doing gate merging. It is also introduced a tool called LOMGAM that does Logic Minimization by Gate Merging. It is generated complex gates by the merging of a set of basic gates with uni
Publikováno v:
System Level Design from HW/SW to Memory for Embedded Systems ISBN: 9783319900223
IESS
IFIP Advances in Information and Communication Technology
5th International Embedded Systems Symposium (IESS)
5th International Embedded Systems Symposium (IESS), Nov 2015, Foz do Iguaçu, Brazil. pp.210-217, ⟨10.1007/978-3-319-90023-0_17⟩
IESS
IFIP Advances in Information and Communication Technology
5th International Embedded Systems Symposium (IESS)
5th International Embedded Systems Symposium (IESS), Nov 2015, Foz do Iguaçu, Brazil. pp.210-217, ⟨10.1007/978-3-319-90023-0_17⟩
Part 5: Embedded HW/SW Design and Applications; International audience; The Izhikevich’s simple model (ISM) for neural activity presents a good compromise between waveform quality and computational cost. FPGAs (Field Programmable Gate Array) are po
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::42ac259bc6fed341d82bdd281d6edfe2
https://doi.org/10.1007/978-3-319-90023-0_17
https://doi.org/10.1007/978-3-319-90023-0_17
Publikováno v:
Communications in Computer and Information Science ISBN: 9783319710105
The objective of this work is to obtain a complete synchronization of Hopfield Neural Networks (HNN) with a delay using a Field Programmable Gate Array (FPGA) simulating in real-time a Natural Neural Networks (NNN). This work is motivated by research
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fc2059382d8d6f071a8372c128e0f999
https://doi.org/10.1007/978-3-319-71011-2_2
https://doi.org/10.1007/978-3-319-71011-2_2
Publikováno v:
ICECS
Understanding and modeling the brain is one of the key scientific challenges in the twenty-first century, and a grown effort is rising on a global scale. Due to its high parallelism, the hardware implementation of large-scale spiking neural networks
Publikováno v:
Biohybrid Systems
Autor:
Diego Neves de Sousa, Marco Terres, Guilherme Bontorin, Marcelo Johann, Roger Llanos, Ricardo Reis
Publikováno v:
PATMOS
Level Shifters (LS) are essential components of integrated circuits with multiple power supply. They work as voltage scaling interfaces between different power domains. In this paper, we present an energy-efficient level shifter with low area topolog
Publikováno v:
LASCAS
Global Routing is one of the major Electronic Design Automation steps and it is classified as an NP-hard problem. We verified that 61% of the nets in ISPD 2008's benchmarks are shorter than 128 length units. We propose a method to cluster these nets