Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Guanwen Zhong"'
Publikováno v:
ACM Transactions on Embedded Computing Systems. 16:1-22
Heterogeneous multiprocessor system-on-chip architectures are endowed with accelerators such as embedded GPUs and FPGAs capable of general-purpose computation. The application developers for such platforms need to carefully choose the accelerator wit
Publikováno v:
CVCBT
The Stratum protocol is the de facto protocol for mining proxies in proof-of-work (PoW) based cryptocurrencies such as Bitcoin. A Stratum mining proxy connects to an upstream mining pool server and to downstream miners through TCP/IP connections. The
Convolutional Neural Networks (CNN) have been widely deployed in diverse application domains. There has been significant progress in accelerating both their training and inference using high-performance GPUs, FPGAs, and custom ASICs for datacenter-sc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::49452c8a7ac60763f84fe4c44d119395
http://arxiv.org/abs/1804.00706
http://arxiv.org/abs/1804.00706
Publikováno v:
IEEE/ACM Design Automation and Test in Europe (DATE'17)
IEEE/ACM Design Automation and Test in Europe (DATE'17), Mar 2017, Lausanne, Switzerland. pp.1141-1146, ⟨10.23919/DATE.2017.7927161⟩
DATE
IEEE/ACM Design Automation and Test in Europe (DATE'17), Mar 2017, Lausanne, Switzerland. pp.1141-1146, ⟨10.23919/DATE.2017.7927161⟩
DATE
International audience; Applications containing compute-intensive kernels with nested loops can effectively leverage FPGAs to exploit fine-and coarse-grained parallelism. HLS tools used to translate these kernels from high-level languages (e.g., C/C-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::778c1298080cd6e89b47c95fd10c71c3
https://hal-uphf.archives-ouvertes.fr/hal-03388558
https://hal-uphf.archives-ouvertes.fr/hal-03388558
Publikováno v:
Emerging Technology and Architecture for Big-data Analytics ISBN: 9783319548395
Heterogeneous computing platforms combining general-purpose processing elements with different accelerators (such as GPU or FPGAs) are ideally suited for efficient processing of compute-intensive data analytics kernels. In this chapter, we focus on t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c010b3c6cfdb8295e79554beda61e7e4
https://doi.org/10.1007/978-3-319-54840-1_2
https://doi.org/10.1007/978-3-319-54840-1_2
Publikováno v:
PDP
25th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP)
25th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP), Mar 2017, St. Petersburg, Russia. pp.85-92, ⟨10.1109/PDP.2017.11⟩
25th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP)
25th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP), Mar 2017, St. Petersburg, Russia. pp.85-92, ⟨10.1109/PDP.2017.11⟩
International audience; Modern System-on-Chip (SoC) designs face many challenges. Choosing the best communication protocol among the different processing nodes is one of the most important design decisions. On-chip communication architectures can hav
Publikováno v:
DAC
The increasing complexity of FPGA-based accelerators, coupled with time-to-market pressure, makes high-level synthesis (HLS) an attractive solution to improve designer productivity by abstracting the programming effort above register-transfer level (
Publikováno v:
IEEE Transactions on Vehicular Technology
IEEE Transactions on Vehicular Technology, Institute of Electrical and Electronics Engineers, 2016, 65 (6), pp.4802-4812. ⟨10.1109/TVT.2016.2546957⟩
IEEE Transactions on Vehicular Technology, Institute of Electrical and Electronics Engineers, 2016, 65 (6), pp.4802-4812. ⟨10.1109/TVT.2016.2546957⟩
International audience; Advanced driver-assistance systems (ADAS) generally embrace heterogeneous platforms consisting of central processing units and field-programmable gate arrays (FPGAs) to achieve higher performance and energy efficiency. The mul
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f8c376aa25d338bf31159f6ddbc092f2
https://hal-uphf.archives-ouvertes.fr/hal-03400598
https://hal-uphf.archives-ouvertes.fr/hal-03400598
Publikováno v:
2014 32nd IEEE International Conference on Computer Design (ICCD)
2014 32nd IEEE International Conference on Computer Design (ICCD), Oct 2014, Seoul, South Korea. pp.456-463, ⟨10.1109/ICCD.2014.6974719⟩
ICCD
2014 32nd IEEE International Conference on Computer Design (ICCD), Oct 2014, Seoul, South Korea. pp.456-463, ⟨10.1109/ICCD.2014.6974719⟩
ICCD
International audience; Real-world applications such as image processing, signal processing, and others often contain a sequence of computation intensive kernels, each represented in the form of a nested loop. High-level synthesis (HLS) enables effic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4ae8495423df357ac3d7711f6ab11870
https://hal-uphf.archives-ouvertes.fr/hal-03386031
https://hal-uphf.archives-ouvertes.fr/hal-03386031
Publikováno v:
ACM Transactions on Embedded Computing Systems; 2017 Special Issue, Vol. 16 Issue 5s, p1-22, 22p