Zobrazeno 1 - 10
of 93
pro vyhledávání: '"Greiner, Alain"'
Autor:
Vivet, Pascal, Guthmuller, Eric, Thonnart, Yvain, Pillonnet, Gaël, Moritz, Guillaume, Miro-Panades, Ivan, Fuguet, Cesar, Durupt, Jean, Bernard, Christian, Varreau, Didier, Pontes, Julian, Thuries, Sebastien, Coriat, David, Harrand, Michel, Dutoit, Denis, Lattard, Didier, Arnaud, Lucile, Charbonnier, Jean, Coudrain, Perceval, Garnier, Arnaud, Berger, Frederic, Gueugnot, Alain, Greiner, Alain, Meunier, Quentin L., Farcy, Alexis, Arriordaz, Alexandre, Cheramy, Severine, Clermidy, Fabien
Publikováno v:
2020 IEEE International Solid-State Circuits Conference-(ISSCC)
2020 IEEE International Solid-State Circuits Conference-(ISSCC), Feb 2020, San Francisco, United States. pp.46-48, ⟨10.1109/ISSCC19947.2020.9062927⟩
2020 IEEE International Solid-State Circuits Conference-(ISSCC), Feb 2020, San Francisco, United States. pp.46-48, ⟨10.1109/ISSCC19947.2020.9062927⟩
International audience; In the context of high performance computing, the integration of more computing capabilities with generic cores or dedicated accelerators for AI application is raising more and more challenges. Due to the increasing costs of a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::08df86ec2b2f65ac2fd786245b437f01
https://hal.archives-ouvertes.fr/hal-02985945
https://hal.archives-ouvertes.fr/hal-02985945
Akademický článek
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Fault-Tolerance Mechanisms for Permanent Failures in a Coherent Shared-Memory Many-Core Architecture
Autor:
Fuguet, César, Greiner, Alain
Publikováno v:
Colloque GDR SoC-SiP
Colloque GDR SoC-SiP, Jun 2014, Paris, France. 2014
Colloque GDR SoC-SiP, Jun 2014, Paris, France. 2014
National audience; Exponential augmentation on the transistor density in nowadays integrated circuits increases probability of faults. This work proposes an "On the field" fault-tolerance strategy for many-core processors allowing self-healing agains
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::19317b033c519890b00968ff5eae4374
https://hal.science/hal-01011990/document
https://hal.science/hal-01011990/document
Publikováno v:
Conférence en Parallélisme, Architecture et Systèmes, ComPAS 2014
Conférence en Parallélisme, Architecture et Systèmes, ComPAS 2014, Apr 2014, Neuchâtel, Suisse
Conférence en Parallélisme, Architecture et Systèmes, ComPAS 2014, Apr 2014, Neuchâtel, Suisse
National audience
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::f4570c70558ed57df8ccc411f1bbf08f
https://hal.archives-ouvertes.fr/hal-01219760
https://hal.archives-ouvertes.fr/hal-01219760
Publikováno v:
DATE 2010-Design, Automation & Test in Europe Conference & Exhibition
DATE 2010-Design, Automation & Test in Europe Conference & Exhibition, Mar 2010, Dresden, Germany. pp.606-609
DATE 2010-Design, Automation & Test in Europe Conference & Exhibition, Mar 2010, Dresden, Germany. pp.606-609
International audience; The simulation speed is a key issue in virtual prototyping of Multi-Processors System on Chip (MPSoCs). The SystemC TLM2.0 (Transaction Level Modeling) approach accelerates the simulation by using Interface Method Calls (IMC)
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::b645ee07db71fe652ca27afbd34a9138
https://hal.archives-ouvertes.fr/hal-00748083
https://hal.archives-ouvertes.fr/hal-00748083
Publikováno v:
FDL Forum on Specification & Design Languages
FDL Forum on Specification & Design Languages, Sep 2009, Nice, France. pp.1-4
FDL Forum on Specification & Design Languages, Sep 2009, Nice, France. pp.1-4
International audience; Streaming applications, such as packet switching or video and multimedia processing, require high through-put, that can be obtained by exploiting the application coarse grain parallelism, and mapping the parallel multitasks ap
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::c7f9571fb5fab75db8f6d87a1d4bb82b
https://hal.archives-ouvertes.fr/hal-01295103
https://hal.archives-ouvertes.fr/hal-01295103
Autor:
Zhang, Zhen, Greiner, Alain
Publikováno v:
Colloque national GDR SOC-SIP
Colloque national GDR SOC-SIP, 2008, Paris, France
Colloque national GDR SOC-SIP, 2008, Paris, France
National audience; Nous avons défini et validé un algorithme de routage reconfigurable pour la tolérance aux fautes dans des NoCs possédant une topologie de type 2D-Mesh. Cet algorithme peut etre utilisé pour toute topologie ayant un routeur ou
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::788e0bcb5dbce13b4b665ed744589bbc
https://hal.archives-ouvertes.fr/hal-00592277/document
https://hal.archives-ouvertes.fr/hal-00592277/document
Publikováno v:
CNFM Coordination Nationale pour la Formation en Micro-nanoélectronique
CNFM Coordination Nationale pour la Formation en Micro-nanoélectronique, Nov 2008, St Malo, France. pp.33-38
CNFM Coordination Nationale pour la Formation en Micro-nanoélectronique, Nov 2008, St Malo, France. pp.33-38
National audience; Nous montrons comment une application simple, mais représentative des applications multimédia et réseau réellement visées est utilisé en enseignement du niveau master pour former les étudiants à la conception au niveau syst
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::d17cbf21e4c7ebaab6ac9545e5b81072
https://hal.archives-ouvertes.fr/hal-01301525
https://hal.archives-ouvertes.fr/hal-01301525
Publikováno v:
2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC); 2016, p61-68, 8p
Autor:
Sheibanyrad, Abbas, Greiner, Alain
Publikováno v:
ESA International Conference on Embedded Systems and Applications
ESA International Conference on Embedded Systems and Applications, Jun 2007, Las Vegas, Nevada, United States. pp.27-33
ESA International Conference on Embedded Systems and Applications, Jun 2007, Las Vegas, Nevada, United States. pp.27-33
International audience; This paper presents three high-throughput low-latency FIFOs that can be used as efficient and reliable interfaces between different domains in hybrid-timing systems. These three hardware components have been designed to be use
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::83f122d1d6094d5b00880e69be7d20f0
https://hal.science/hal-01311526
https://hal.science/hal-01311526