Zobrazeno 1 - 10
of 10
pro vyhledávání: '"Gregory Costrini"'
Autor:
David L. Rath, Rainer Florian Schnabel, T. Joseph, Kenneth P. Rodbell, Lynne Gignac, R. G. Filippi, X.J Ning, Chenming Hu, Gregory Costrini, Timothy D. Sullivan, Stefan Weber, G. Stojakovic, Lawrence A. Clevenger, Edward W. Kiewra, Roy C. Iggulden, M. Gribelyuk, R.V.S.S.N. Ravikumar, T. Kane, Jeff Gambino
Publikováno v:
Thin Solid Films. 388:303-314
The electromigration behavior and microstructural features of AlCu Dual Damascene lines are compared to those of AlCu metal reactively ion etched (RIE) lines. Test structures consist of 0.18-, 0.35- and 1.33-μm-wide lines terminated by W diffusion b
Autor:
Gregory Costrini, J. D. Baniecki, M. Wise, Laertis Economikos, Satish D. Athavale, J. Lian, N. Nagel
Publikováno v:
Integrated Ferroelectrics. 38:259-267
Three dimensional integration of BSTO thin films for Gigabit DRAM application is performed by a MOCVD BST process combined with a high temperature barrier stack of TaSiN/Ir/IrO2 with SiO2 sidewall protection. The SiO2 layer is formed by a new low tem
Autor:
D. Tobben, G.Y. Lee, Roy C. Iggulden, Stefan J. Weber, Maria Ronay, Jeff Gambino, Zhijian Lu, R.F. Schnabel, Clevenger Leigh Anne H, Gregory Costrini, R. Ramachandran, X.J. Ning, R. G. Filippi, Chenting Lin, David M. Dobuzinsky
Publikováno v:
Microelectronic Engineering. 50:265-270
This paper presents an overview of issues associated with Al dual damascene process technology. Different integration schemes are discussed and characteristics of metal fill, planarization and reliability are highlighted. Finally, a comparison is mad
Autor:
Basanth Jagannathan, D. Faken, N. Zhan, Manoj Kumar, B. Cipriany, James P. Norum, K. Greiner, S. Breit, Karen A. Nummy, D. Fried, Shreesh Narasimha, B. Zhang, Rajeev Malik, Paul D. Agnello, Gregory Costrini, J. Meiring, Katsunori Onishi, H. Nanjundappa, Ahmed N. Noemaun, Christopher D. Sheraw, Stephen S. Furkay
Publikováno v:
2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).
We present a technology development methodology that relies on 3D virtual fabrication to rapidly improve yield by increasing tolerance to multilevel process variation. This methodology has been successfully implemented in the development and yield ra
Autor:
Jinghong Li, Henry K. Utomo, Chun-Yung Sung, Andres Bryant, Qiqing Ouyang, Min Yang, Horatio S. Wildman, N. Klymko, David M. Fried, Massimo V. Fischetti, Gregory Costrini, Siddhartha Panda, Thomas S. Kanarsky, John A. Ott, Judson R. Holt, Huajie Chen, Meikei Ieong, Nivo Rovedo
Publikováno v:
Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..
CMOS devices with embedded SiGe source/drain for pFETs and tensile stressed liner for nFETs have been demonstrated for the first time on hybrid orientation substrates. Ring oscillators have also been fabricated. Significant performance improvement is
Autor:
L. Economikos, Andres Bryant, D. Degraw, Munir D. Naeem, Chun-Yung Sung, Woo-Hyeong Lee, L. Black, Christopher D. Sheraw, Meikei Ieong, Yujun Li, Siddhartha Panda, Shih-Fen Huang, Massimo V. Fischetti, Judson R. Holt, Victor Chan, Thomas S. Kanarsky, Dureseti Chidambarrao, Renee T. Mo, Gregory Costrini, David M. Fried, J. Groschopf, Mukesh Khare, Xinhui Wang, Scott Luning, A. Bonnoit, D. Brown, A. Kapur, Min Yang, Paul D. Agnello, X. Chen
Publikováno v:
Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..
Hybrid orientation technology (HOT) has been successfully integrated with a dual stress liner (DSL) process to demonstrate outstanding PFET device characteristics in epitaxially grown [110] bulk silicon. Stress induced by the nitride MOL liners resul
Autor:
Stefan J. Weber, M. Hug, F. Zach, R. G. Filippi, K.P. Muller, J. Gambino, R.F. Schnabel, J.F. Nuetzel, Carl J. Radens, R. Iggulden, G. Mueller, Gary B. Bronner, Chenting Lin, David M. Dobuzinsky, Gregory Costrini, Larry Clevenger
Publikováno v:
1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).
A novel interconnect scheme is presented which has been used to significantly reduce the chip size of an 1 Gb SDRAM chip. The key element is the use of slotted vias for low resistance horizontal interconnects. This allows us to combine low capacitanc
Autor:
Daniel C. Edelstein, William J. Cote, C. Osborn, V. Sardesai, Gary B. Bronner, Gregory Costrini, D. Poindexter
Publikováno v:
1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).
This paper presents results evaluating the impact of copper (Cu) wiring on a production 64 Mb/0.35 /spl mu/m trench capacitor DRAM technology. There has been considerable progress integrating Cu wiring into high performance logic processes, but littl
Autor:
Keith T. Kwietniak, Y. Limb, Katherine L. Saenger, M.L. Wise, Deborah A. Neumayer, Gregory Costrini, P. C. Andricacos, J. D. Baniecki, J. Lian, Cyril Cabral, Robert B. Laibowitz, Satish D. Athavale
Publikováno v:
MRS Proceedings. 655
Materials requirements for electrodes and barriers in high density dynamic random access memory (DRAM) and ferroelectric random access memory (FERAM) are reviewed, and some approaches to barrier materials and device geometries are described. Electrod
Publikováno v:
Journal of The Electrochemical Society. 148:C758
A through-mask electroplating process is described for forming Pt electrode structures with the vertical sidewalls and submicrometer dimensions desired for dynamic random access memory applications. The plating process used an aqueous KOH-based solut