Zobrazeno 1 - 10
of 26
pro vyhledávání: '"Gopal Raut"'
Publikováno v:
IEEE Access, Vol 12, Pp 43600-43614 (2024)
In response to the escalating demand for hardware-efficient Deep Neural Network (DNN) architectures, we present a novel quantize-enabled multiply-accumulate (MAC) unit. Our methodology employs a right shift-and-add computation for MAC operation, enab
Externí odkaz:
https://doaj.org/article/a5f8400cabdf4dc8be9e44a2a7af5fc8
Publikováno v:
IEEE Access, Vol 11, Pp 34912-34924 (2023)
This article present a highly efficient and performance-enhanced Softmax Function (SF) designed for a deep neural network accelerator. The SF is an essential component of deep learning models, primarily used in the classification layer, and also in h
Externí odkaz:
https://doaj.org/article/a10506300c3341a3b5491e67b2035c12
Publikováno v:
e-Prime: Advances in Electrical Engineering, Electronics and Energy, Vol 4, Iss , Pp 100157- (2023)
In this paper problem is addressed in the current study by providing resource-efficient CORDIC enabled neuron architecture (RECON) that can be customized to calculate both block of multiply-accumulate (MAC) unit and non-linear activation function (AF
Externí odkaz:
https://doaj.org/article/df33d0526075407cbc5efc11ad5d984a
Publikováno v:
IEEE Open Journal of Circuits and Systems, Vol 2, Pp 170-181 (2021)
Contemporary hardware implementations of artificial neural networks face the burden of excess area requirement due to resource-intensive elements such as multiplier and non-linear activation functions. The present work addresses this challenge by pro
Externí odkaz:
https://doaj.org/article/36ab3e3978ca419490598ca4cc4b0653
Publikováno v:
IEEE Open Journal of Circuits and Systems, Vol 2, Pp 292-292 (2021)
In [1], citations are placed incorrectly in Table 5 and Table 6. Citation numbers have been revised as follows: In Table 5 [22] should be [17], [23] should be [22], and [21] should be [20].In Table 6 [25] should be [24] and [26] should be [25].
Externí odkaz:
https://doaj.org/article/ff1497a96ca047b7a58f8ee2d8311b0f
Publikováno v:
Circuits, Systems, and Signal Processing.
Publikováno v:
ACM Transactions on Reconfigurable Technology and Systems.
Practical implementation of deep neural networks (DNNs) demands significant hardware resources, necessitating high computational power and memory bandwidth. While existing FPGA-based DNN accelerators are primarily optimized for fast single-task perfo
Autor:
Gopal Raut, Narendra Singh Dhakad, Neha Gupta, Anton Biasizzo, Gregor Papa, Santosh Kumar Vishvakarma
Publikováno v:
Neurocomputing
Neurocomputing, 2021.
Neurocomputing, 2021.
Despite many decades of research on high-performance Deep Neural Network (DNN) accelerators, their massive computational demand still requires resource-efficient, optimized and parallel architecture for computational acceleration. Contemporary hardwa
Publikováno v:
Circuits, Systems, and Signal Processing. 41:2045-2060
Autor:
Pranose J Edavoor, Aneesh Raveendran, David Selvakumar, Vivian Desalphine, Dharani Shankar G, Gopal Raut
Publikováno v:
2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID).