Zobrazeno 1 - 10
of 39
pro vyhledávání: '"Gonzalo Duchen"'
Autor:
José Rangel, Esteban Anides, Eduardo Vázquez, Giovanny Sanchez, Juan-Gerardo Avalos, Gonzalo Duchen, Linda K. Toscano
Publikováno v:
Mathematics, Vol 12, Iss 22, p 3472 (2024)
During the last years, the demand for internet-of-things (IoT) resource-constrained devices has grown exponentially. To address this need, several digital methods have been proposed to improve these devices in terms of area and power consumption. Des
Externí odkaz:
https://doaj.org/article/7fdd4f77d33e4392ae3c5f60f477b081
Autor:
Angel Vazquez, Luis Garcia, Karina Toscano, Juan-Carlos Sanchez, Gonzalo Duchen, Hector Perez, Juan-Gerardo Avalos, Giovanny Sanchez
Publikováno v:
Neurocomputing. 503:1-16
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d54685571f3168c3684d32c3f28d3ec8
https://doi.org/10.1016/j.neucom.2022.06.109
https://doi.org/10.1016/j.neucom.2022.06.109
Autor:
Gonzalo Duchen Sanchez, Basilio Del Muro Cuellar, Juan Francisco Marquez Rubio, Martin Velasco Villa, Miguel Angel Hernandez Perez
Publikováno v:
IEEE Latin America Transactions. 20:291-300
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e857509c39a1b2291e7b3441fa5bc719
https://doi.org/10.1109/tla.2022.9661469
https://doi.org/10.1109/tla.2022.9661469
Autor:
Enrique Escamilla Hemández, Víctor Kravchenko, Volodymyr Ponomaryov, Gonzalo Duchen Sánchez, David Hernández Sánchez
Publikováno v:
Revista Facultad de Ingeniería Universidad de Antioquia, Iss 55, Pp 134-143 (2010)
El presente artículo muestra la puesta en práctica de hardware para realizar el procesamiento en tiempo real de la señal de radar usando una técnica simple, rápida basada en arquitectura de FPGA (Field Programmable Gate Array). El proceso incluy
Externí odkaz:
https://doaj.org/article/bbf4b0bb8bc64515bb453004865b9373
Autor:
Enrique Escamilla Hernández, Víctor Kravchenko, Volodymyr Ponomaryov, Gonzalo Duchen Sánchez, David Hernández Sánchez
Publikováno v:
Revista Facultad de Ingeniería Universidad de Antioquia, Iss 55 (2013)
We present the hardware implementation of radar real time processing procedures using a simple, fast technique based on FPGA (Field Programmable Gate Array) architecture. This processing includes different window procedures during pulse compression i
Externí odkaz:
https://doaj.org/article/5554ffac7caa4a0c9951415bb450fffe
Autor:
Hector Perez, Gabriel Sánchez, Gonzalo Duchen, Juan Gerardo Avalos, Giovanny Sánchez Rivera, Carlos Díaz
Publikováno v:
IEEE Latin America Transactions. 16:1524-1531
In recent years, the scientific community's interest for developing software or hardware tools capable of processing and displaying real-time simulations of large-scale Spiking Neural Networks (SNN) has been growing exponentially. Visualization of th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4ae23cf25f917457f8d3a4c3d46cdd64
https://doi.org/10.1109/tla.2018.8408450
https://doi.org/10.1109/tla.2018.8408450
Autor:
Gonzalo Duchen, Carlos Daniel Vázquez, B. del Muro, Juan Francisco Márquez, David Novella, Miguel Hernandez
Publikováno v:
IFAC-PapersOnLine. 51:432-437
This paper considers the problem of stabilization and control of linear time invariant high order systems with one or two unstable real poles, n real stable poles plus time-delay. In order to ensure a stable behavior of the closed loop system, necess
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bd63844b02dabdf01e3e20ddd46125f5
https://doi.org/10.1016/j.ifacol.2018.06.133
https://doi.org/10.1016/j.ifacol.2018.06.133
Publikováno v:
Neurocomputing. 238:152-156
The Spiking Neural P (SN P) system is defined as a type of parallel computing mechanism bio-inspired by the behavior of the soma. Several authors have been employing these systems in order to create efficient arithmetic divisor circuits exploiting at
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8994bd97c80d71fa9f746dbfb5459e7d
https://doi.org/10.1016/j.neucom.2017.01.046
https://doi.org/10.1016/j.neucom.2017.01.046
Publikováno v:
Neurocomputing. 239:113-121
High performance spiking neural multiplier.Parallel input data processing in SN P systems.Scalable parallel architecture based on SN P systems. In the last 10 years, there has been a considerable increase in the number of studies on the development o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cd89a0af2efb3395d4a2873d25efc598
https://doi.org/10.1016/j.neucom.2017.02.009
https://doi.org/10.1016/j.neucom.2017.02.009
Publikováno v:
Neurocomputing. 189:130-134
We propose a novel unary spiking circuit for a serial multiplier with variable dendritic delays. Serial multipliers commonly use the soma model for the arithmetic operation. The structure of the serial multiplier and the efficient implementation of t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bdd2bd91c2bb1f9bd7831b9f98e961ff
https://doi.org/10.1016/j.neucom.2015.12.086
https://doi.org/10.1016/j.neucom.2015.12.086