Výsledky vyhledávání - "Gong-Heum Han"

A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process

Publikováno v: 2022 IEEE International Solid- State Circuits Conference (ISSCC).

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::a10249d70b36afa2ce068eb468610e20
https://doi.org/10.1109/isscc42614.2022.9731537

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Industry's First 7.2 Gbps 512GB DDR5 Module

Publikováno v: HCS

Spurred by the increasing market needs for big data and cloud services, global server suppliers and hyper- scalers are looking to adopt high-speed and large-capacity memory modules. To fulfill this trend, the brand- new low-voltage operable DDR5 (dou

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::b11020a906b84875c0db7f11e6307978
https://doi.org/10.1109/hcs52781.2021.9567190

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A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking

Publikováno v: IEEE Journal of Solid-State Circuits. 54:197-209

The graphic DRAM standard GDDR6 is developed to overcome the limitation of previous standards GDDR5/5X for achieving high-speed operation. This paper introduces 16-Gb GDDR6 DRAM with a per-bit trainable single-ended decision feedback equalizer (DFE),

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::7d08bc4f852cc052f17c7e89b51e1192
https://doi.org/10.1109/jssc.2018.2883395

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A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

Publikováno v: ISSCC

Starting at 512Mb 6Gb/s/pin [1], GDDR5's speed and density have been steadily developing for about 10 years; recently achieving 8Gb 9Gb/s/pin [2] with per-pin timing training. Although 8Gb GDDR5X can operate at 12Gb/s [3] by increasing the burst leng

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::0b3314102637da5c0ef4d2bd3d784505
https://doi.org/10.1109/isscc.2018.8310255

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23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices

Publikováno v: ISSCC

With the growth of wearable devices, such as smart watches and smart glasses, there is an increasing demand for lower power dissipation, to achieve longer battery life with limited battery capacity. Nevertheless, memory bandwidth needs to increase to

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::c0f825e2862316ff32770b6cc4b7d7eb
https://doi.org/10.1109/isscc.2017.7870427

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25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation

Publikováno v: ISSCC

The recent revolution in handheld computing with high-speed cellular network made mobile processors have multi-cores and powerful 3D graphic engines that support FHD (1920×1080) or even higher resolutions. Consequently, the memory bandwidth requirem

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::c9290d1d68fcad2afd51d8078cddaebc
https://doi.org/10.1109/isscc.2014.6757500

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64Mb mobile stacked single-crystal Si SRAM (S/sup 3/RAM) with selective dual pumping scheme (SDPS) and multi cell burn-in scheme (MCBS) for high density and low power SRAM

Autor: Bo-Tak Lim, Jong-Pil Son, Hung-Jun An, Kyung-Hee Kim, Hyun-Sun Mo, Gong-Heum Han, Hyou-Youn Nam, Joon-Min Park, Hyun-Geun Byun, Su-Yeon Kim, Choong-keun Kwak, Sang-beom Kang

Publikováno v: 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

A 64Mb Mobile S/sup 3/RAM was designed with stacked single-crystal thin film transistor (SSTFT) cell using 80nm SRAM technology to overcome chip size penalty of conventional 6T-SRAM with improved performance. For 1.3V operation, word line (WL) and ce

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::353872c04ef2d361058036c963f3cd94
https://doi.org/10.1109/vlsic.2004.1346588

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Conference

64Mb mobile stacked single-crystal Si SRAM (S3RAM) with selective dual pumping scheme (SDPS) and multi cell burn-in scheme (MCBS) for high density and low power SRAM.

Autor: Hung-Jun An, Hyou-youn Nam, Hyun-sun Mo, Jong-pil Son, Bo-tak Lim, Sang-beom Kang, Gong-heum Han, Joon-min Park, Kyung-hee Kim, Su-yeon Kim, Choong-keun Kwak, Hyun-geun Byun

Publikováno v: 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525); 2004, p282-283, 2p

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