Zobrazeno 1 - 10
of 21
pro vyhledávání: '"Gilroy Vandentop"'
Autor:
Manish Chandhok, Gilroy Vandentop, Micahel J. Leeson, E. Steve Putna, Grant M. Kloster, Uday Shah, Todd R. Younkin
Publikováno v:
Journal of Photopolymer Science and Technology. 24:127-136
Extreme Ultraviolet (EUV) lithography is a leading technology option for manufacturing at the 22nm half pitch node and beyond. Implementation of the technology will require continued progress on several key supporting infrastructure challenges, inclu
Publikováno v:
13th InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems.
With the continuous scaling of low k dielectric in multicore processors, the intrinsic CTE mismatch between a Si die (CTE: 2.3 ppm/°C) and an organic substrate (16–18 ppm/°C) brings a susceptibility for more failures. There are limited successes
Autor:
Kazuo Tawarayama, Hajime Aoyama, Tetsunori Murachi, Gilroy Vandentop, Takashi Kamo, Yukiyasu Arisawa, Yashesh Shroff, Toshihiko Tanaka, Ichiro Mori, Alan Myers, Yuusuke Tanaka, Taiga Uno
Publikováno v:
SPIE Proceedings.
This paper describes the critical dimension (CD) accuracy of metal-layer patterns for the 15-nm logic node and beyond replicated with model-based optical proximity correction, flare variation compensation, and shadowing effect correction. The model f
Autor:
Gilroy Vandentop, Ernisse Putna, Tetsunori Murachi, Alan Myers, Manish Chandhok, Steven L. Carson, James S. Clarke, Todd R. Younkin, Ted Liang, Michael J. Leeson, Guojing Zhang
Publikováno v:
Alternative Lithographic Technologies.
EUV lithography is considered one of the options for high volume manufacturing (HVM) of 16 nm MPU node devices [1]. The benefits of high k1(~0.5) imaging enable EUVL to simplify the patterning process and ease design rule restrictions. However, EUVL
Autor:
Pei-yang Yan, Barry Lieberman, Ted Liang, Emily Y. Shu, Seh-Jin Park, Guojing Zhang, Ping Qu, Alan R. Stivers, Gilroy Vandentop, Sven Henrichs, Erdem Ultanir, Peter Sanchez
Publikováno v:
SPIE Proceedings.
Extreme ultraviolet lithography (EUVL) tool development achieved a big milestone last year as two full-field Alpha Demo Tools (ADT) were shipped to customers by ASML. In the future horizon, a full field "EUV1" exposure tool from Nikon will be availab
Autor:
Seh-Jin Park, Guojing Zhang, Alan Myers, Gilroy Vandentop, Alan R. Stivers, Ted Liang, Patrick P. Naulleau
Publikováno v:
SPIE Proceedings.
Mask defect specifications not only are needed to ensure quality masks for acceptable resist patterning on wafers, but also are utilized as a common goal for tool development, noticeably for mask inspection and repair. Defect specifications are gener
Autor:
Chang Ju Choi, Emily Y. Shu, Seh-Jin Park, Eric J. Lanzendorf, Guojing Zhang, Alan R. Stivers, Gilroy Vandentop, Kangmin Hsia, Peter Sanchez, Jeff Farnsworth, Manish Chandhok, Pei-yang Yan, Michael J. Leeson, Yan Du, Ted Liang
Publikováno v:
SPIE Proceedings.
It becomes increasingly important to have an integrated process for Extreme UltraViolet (EUV) mask fabrication in order to meet all the requirements for the 32 nm technology node and beyond. Intel Corporation established the EUV mask pilot line by in
Autor:
Brandon Barnett, Gilroy Vandentop, Henning Braunisch, Ian A. Young, Daoqiang Lu, Steven Towle, Edris M. Mohammed, Thomas P. Thomas
Publikováno v:
SPIE Proceedings.
We describe the development of a high-speed, 12-channel (8-data, 2-clock and 2-alignment channels), parallel optical link with a unique packaging concept. The package is used to demonstrate the viability of chip-to-chip optical I/O in very large scal
Publikováno v:
52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345).
The bumpless build-up layer (BBUL) microelectronic packaging technology is characterized by the absence of a conventional substrate core and a direct extension of the outmost metallization layers of the die into the overall thin substrate. Such a cor
Publikováno v:
Packaging, Reliability and Manufacturing Issues Associated With Electronic and Photonic Products.
Bumpless Build-Up Layer (BBUL) is a novel package developed to meet future packaging technology requirements. The BBUL package provides the advantages of small electrical loop inductance and reduced thermomechanical stresses on low dielectric constan