Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Gillis Winderickx"'
Publikováno v:
2018 IEEE 20th Electronics Packaging Technology Conference (EPTC).
This paper presents the fabrication of a SiN y -based photonic integrated circuit (PIC) on top of a CMOS imager sensor (CIS) using semiconductor post processing fabrication technology. The photonic key components consists of SiN y optical waveguides
Autor:
Woochang Lee, Simone Severi, Pol Van Dorpe, H. K. Tyagi, Xavier Rottenberg, Tom Claes, Sungmo Ahn, Maurine Malak, Victor Garcia-Munoz, Peter Peumans, Gillis Winderickx, Rita Van Hoof, Harrie Tilmans, Dongho Kim
Publikováno v:
2018 IEEE Micro Electro Mechanical Systems (MEMS).
Herein, we report about the monolithic integration of a unique photonic stack on top of a CMOS imager using a dedicated fabrication process. The system key components consists of silicon nitride (SiNy) optical waveguides, sloped input mirror, grating
Autor:
Sonja Sioncke, David P. Brunco, Hugo Bender, Marc Heyns, Sven Van Elshocht, Paul Mertens, Thierry Conard, M. Scarozza, Karl Opsomer, Ali Pourghaderi, Michel Houssa, Gillis Winderickx, Ravi M. Todi, Roger Loo, Krtistien De Meyer, Matty Caymax, G. Nicholas, Koen Martens, Benny Van Daele, Florence Bellenger, Ben Kaczer, Frederik Leys, Paul Zimmerman, J. Van Steenbergen, Annelies Delabie, Trudo Clarysse, Eddy Simoen, Laurent Souriau, Daniel Nelis, Valentina Terzieva, A. Benedetti, Renaud Bonzom, Guy Brammertz, M. Meuris, Cedric Huyghebaert, A. Satta, Wilfried Vandervorst, B. De Jaegar, David Hellin
Publikováno v:
ECS Transactions. 3:783-787
Passivation of the channel in the gate stack is the most important problem for introducing another material than silicon into the channel of CMOS devices. In order to compare the mobility values of different passivation techniques, we propose to use
Autor:
Gustaaf Borghs, Stefan Degroote, Jan Van Steenbergen, Maarten Leys, Marc Meuris, Guy Brammertz, Yves Mols, Matty Caymax, Gillis Winderickx
Publikováno v:
ECS Transactions. 3:585-591
We are reporting on a growth procedure for selective growth of GaAs on Ge substrates by organometallic vapor phase deposition. The precursors used for the growth are Tertiarybutylarsine (TBAs) and Trimethylgallium (TMGa). As a mask material 200 nm th
Autor:
Fabrice Letertre, G. Raskin, M.M. Heyns, T. Billon, Renaud Bonzom, Gillis Winderickx, B. De Jaeger, O. Richard, Frederik Leys, J. Van Steenbergen, Marc Meuris, E. Van Moorhem
Publikováno v:
Microelectronic Engineering. 80:26-29
A key challenge in the engineering of Ge MOSFETs is to develop a proper Ge surface passivation technique prior to high-k dielectric deposition to obtain low interface state density and high carrier mobility. In this work, we optimise a thin, epitaxia
Publikováno v:
IEEE Electron Device Letters. 23:191-193
Metal-insulator-metal (MIM) capacitors with PECVD nitride exhibit trap-induced dispersive behavior, which leads to degradation in capacitor linearity at low frequencies, limiting the accuracy in precision analog circuits. While LPCVD oxide results in
Autor:
T. Vandeweyer, K. De Meyer, Ngoc Duy Nguyen, Patrick Ong, S. Van Huylenbroeck, Stefaan Decoutere, W. Lee, Rafael Venegas, D. Radisic, A. Sibaja-Hernandez, Gillis Winderickx, Shuzhen You
Publikováno v:
2009 IEEE Bipolar/BiCMOS Circuits and Technology Meeting.
An improved fully self-aligned SiGe:C HBT architecture featuring a single-step epitaxial collector-base process is described. An f MAX value of 400GHz is reached by structural as well as intrinsic advancements made to the HBT device.
Autor:
Koen Martens, Roger Loo, Jing-Cheng Lin, Gillis Winderickx, M.M. Heyns, E. Vrancken, B. De Jaeger, Frederik Leys, Geert Eneman, K. De Meyer, Denis Shamiryan, T. Vandeweyer, C.H. Yu, Jerome Mitard, Matty Caymax, Marc Meuris, Luigi Pantisano, David P. Brunco, Geert Hellings
Publikováno v:
2008 IEEE International Electron Devices Meeting.
We report on a 65 nm Ge pFET with a record performance of Ion = 478muA/mum and Ioff,s= 37nA/mum @Vdd= -1V. These improvements are quantified and understood with respect to halo/extension implants, minimizing series resistance and gate stack engineeri
Autor:
Karl Opsomer, Andre Stesmans, Matty Caymax, B. De Jaeger, M.M. Heyns, Lars-Ake Ragnarsson, Frederik Leys, David P. Brunco, G. Nicholas, Gillis Winderickx, Paul Zimmerman, Marc Meuris, Ben Kaczer
Publikováno v:
2006 International Electron Devices Meeting.
Ge pMOS mobilities up to 358 cm2/Vs are demonstrated using a Si-compatible process flow without the incorporation of strain. EOT is approximately 12 Aring with a gate leakage less than 0.01 A/cm 2 at Vt+ 0.6 V. Ge transistors are characterized with g
Autor:
Stefan Kubicek, G. Raskin, B. De Jaeger, M.M. Heyns, Ben Kaczer, Thomas Chiarella, Thierry Conard, Ivo Teerlinck, Sun-Ghil Lee, Matty Caymax, Alessandra Satta, Valery V. Afanas'ev, K. De Meyer, J. Van Steenbergen, J. Poortmans, P. Mijlemans, Serge Biesemans, Wilfried Vandervorst, Paul W. Mertens, Marc Schaekers, Robin Degraeve, Lars-Ake Ragnarsson, Eddy Kunnen, JL Autran, Tom Schram, Erik Sleeckx, S. Van Elshocht, Annelies Delabie, M. Meuris, Michel Houssa, Richard Lindsay, G. Kota, Werner Boullart, J. Croon, E. Van Moorhem, Gillis Winderickx, Andre Stesmans, Peter Verheyen
Publikováno v:
Scopus-Elsevier
34th European Solid-State Device Research Conference (ESSDERC 2004), SEP 21-23, 2004, Leuven, BELGIUM
ESSDERC 2004: PROCEEDINGS OF THE 34TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE
34th European Solid-State Device Research Conference (ESSDERC 2004), SEP 21-23, 2004, Leuven, BELGIUM
ESSDERC 2004: PROCEEDINGS OF THE 34TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE
We report for the first time on deep sub-micron Ge pFETs with physical gate lengths down to 0.151 /spl mu/m. The devices are made using a silicon-like process flow, with a directly etched gate stack consisting of TaN gate on an ALD or MOCVD HfO/sub 2