Zobrazeno 1 - 10
of 99
pro vyhledávání: '"Gil-Cho Ahn"'
Autor:
Jae-Hyuk Lee, Seung-Hoon Lee, Jun-Ho Boo, Jun-Sang Park, Tai-Ji An, Hee-Wook Shin, Young-Jae Cho, Michael Choi, Jin-Wook Burm, Gil-Cho Ahn
Publikováno v:
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE. 23:118-127
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 70:401-405
Autor:
Ho-Jin Kim, Seung-Hoon Lee, Jun-Ho Boo, Jae-Hyuk Lee, Jun-Sang Park, Tai-Ji An, Sung-Han Do, Young-Jae Cho, Michael Choi, Gil-Cho Ahn
Publikováno v:
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE. 21:449-458
Autor:
Hyoung-Jung Kim, Jae-Hyuk Lee, Jae-Geun Lim, Jun-Ho BOO, Ho-Jin Kim, Seong-Bo Park, Youngdon Choi, Jung-Hwan Choi, Gil-Cho Ahn
Publikováno v:
2022 19th International SoC Design Conference (ISOCC).
Autor:
Sung-Han Do, Michael Choi, Seung-Hoon Lee, Yoon-Bin Im, Young Jae Cho, Je-Min Jeon, Jae-Geun Lim, Gil-Cho Ahn, Jae Hyuk Lee, Jun-Ho Boo
Publikováno v:
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE. 21:255-262
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 68:1645-1649
This brief presents a second-order discrete-time (DT) modified feed-forward (FF) delta-sigma modulator. To reduce the attenuation of the quantizer’s input signal due to switched-capacitor (SC) passive summing, the proposed modulator eliminates the
Autor:
Ho-Jin Kim, Kang-Il Cho, Gil-Cho Ahn, Seung-Hoon Lee, Jun-Ho Boo, Yong-Sik Kwak, Jae-Geun Lim
Publikováno v:
IEEE Journal of Solid-State Circuits. 56:1197-1206
This article presents a single-trim switched capacitor (SC) CMOS bandgap reference (BGR) for battery monitoring applications. For a single-temperature trimming, $\beta $ -compensation and curvature correction techniques are employed to minimize non-p
Publikováno v:
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE. 20:99-104
Publikováno v:
2021 IEEE Asian Solid-State Circuits Conference (A-SSCC).
Publikováno v:
Electronics Letters. 56:119-121
A 12 b 50 MS/s successive-approximation register (SAR) ADC with a highly linear C-R hybrid DAC is presented. The proposed DAC significantly reduces the required total number of unit capacitors by processing the upper bits based on a binary-weighted c