Zobrazeno 1 - 10
of 40
pro vyhledávání: '"Gijung Ahn"'
Publikováno v:
IEEE Journal of Solid-State Circuits. 39:795-803
A quad-channel 0.6-3.2 Gb/s/channnel transceiver using eight independent phase-locked loops (PLLs) shows a 1-ps rms random jitter performance without interchannel interference. The PLL employs a folded starved inverter with high supply/substrate nois
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b133cc1a6c500a5839c879546860387d
https://doi.org/10.1109/jssc.2004.826311
https://doi.org/10.1109/jssc.2004.826311
Autor:
Youngdon Choi, Moon-Sang Hwang, Sungioon Kim, Sang-Hyun Lee, Wonchan Kim, Young June Park, Yongsam Moon, Gijung Ahn, Bongjoon Lee, Deog-Kyoon Jeong
Publikováno v:
IEEE Journal of Solid-State Circuits. 37:1822-1830
This paper describes a clock/data recovery circuit (CDR) incorporating a variable-interval 3/spl times/-oversampling method for enhanced high-frequency jitter tolerance. The CDR traces the eye-opening region to place the data-sampling clock exactly a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::0f7a63bf0c6dba02a8eb3de0d60c2efb
https://doi.org/10.1109/jssc.2002.804342
https://doi.org/10.1109/jssc.2002.804342
Publikováno v:
IEEE Journal of Solid-State Circuits. 36:1974-1983
For generation of the multiphase clocks for a serializer, a wide-range multiphase delay-locked loop (DLL) is used in the transmitter to avoid the detrimental characteristics of a phase-locked loop (PLL), such as jitter peaking and accumulated phase e
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5b7bd5cb10fa54e5f2bce144d0ef5de5
https://doi.org/10.1109/4.972148
https://doi.org/10.1109/4.972148
Publikováno v:
IEEE Journal of Solid-State Circuits. 35:915-918
A large-swing, voltage-mode driver and an on-chip termination circuit are presented for high-speed nonreturn-to-zero (NRZ) data transmission through a copper cable. The proposed driver with active pull-up and pull-down can generate a 700-mV signal to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::02cac65f8cb7247643bb5605f4896493
https://doi.org/10.1109/4.845196
https://doi.org/10.1109/4.845196
Publikováno v:
IEEE Journal of Solid-State Circuits. 29:978-981
A new high-density DRAM cell concept is proposed and experimentally demonstrated. This cell, composed of two transistors and one capacitor, generates a large bit line signal with a small cell capacitance during the read cycle. Since it does not need
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c266de1a4dc17f2624da39dc2abf6f40
https://doi.org/10.1109/4.297707
https://doi.org/10.1109/4.297707
Publikováno v:
ISSCC
A multi-rate transceiver incorporating TX slew control with >2times range, PLL with
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::865f84a73254beec36aeaaecc123a305
https://doi.org/10.1109/isscc.2006.1696053
https://doi.org/10.1109/isscc.2006.1696053
Publikováno v:
ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
A low-jitter 5000ppm spread-spectrum clock generator is implemented in a 0.18/spl mu/m CMOS process. By using 10 multi-phase clocks and a /spl Delta//spl Sigma/ modulator with periodic input, the chip has a deterministic jitter of 25ps due to spread-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::156f5cda01db077b8660cc164cc54475
https://doi.org/10.1109/isscc.2005.1493919
https://doi.org/10.1109/isscc.2005.1493919
Publikováno v:
Proceedings of 1994 IEEE Symposium on VLSI Circuits.
This paper describes a CMOS serial link allowing fully duplexed 1 Gbaud serial data communication. The bidirectional serial link comprises a transmitter, a bidirectional bridge, an impedance matching circuit, a 4 GHz data oversampler, and a digital P
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::acf1fc3af618f64d6c2e43b5c7b2c766
https://doi.org/10.1109/vlsic.1994.586248
https://doi.org/10.1109/vlsic.1994.586248
Autor:
Gijung Ahn, Deog-Kyoon Jeong
Publikováno v:
ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361).
This paper presents a 1.25-GBaud transceiver chip implemented with 0.35-/spl mu/m CMOS technology, which can be used as an IEEE 802.32 Gigabit Ethernet 1000Base-X physical layer. A voltage mode driver and an on-chip termination circuit reduce signal
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5dd00891268760b85d2d8053171b5065
https://doi.org/10.1109/icvc.1999.820937
https://doi.org/10.1109/icvc.1999.820937
Publikováno v:
2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c986c445dea5987f0f4521d058bbc5ec
https://doi.org/10.1109/isscc.2001.912608
https://doi.org/10.1109/isscc.2001.912608