Zobrazeno 1 - 10
of 126
pro vyhledávání: '"Gi-Joon Nam"'
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 41:3503-3514
Publikováno v:
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design.
Publikováno v:
Journal of Vacuum Science & Technology B. 41:033201
Nondestructive technology (NDT) is the most popular method for detecting defects inside an object without harming it. A 3D tomography algorithm toolbox and an x-ray imaging system are the essential components of NDT. We fabricated a high-resolution c
Publikováno v:
2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD).
Publikováno v:
ACM Transactions on Design Automation of Electronic Systems. 24:1-17
This article presents an algorithm for integrated timing-driven latch placement and cloning. Given a circuit placement, the proposed algorithm relocates some latches while circuit timing is improved. Some latches are replicated to further improve the
Publikováno v:
DATE
Owing to the inherent fault tolerance of deep neural networks (DNNs), many structural faults in DNN accelerators tend to be functionally benign. In order to identify functionally critical faults, we analyze the functional impact of stuck-at faults in
Autor:
Hua Xiang, Jinwook Jung, Vishnavi Chauha, Rongjian Liang, Jiang Hu, Gi-Joon Nam, Zhiyao Xie, Yi Chen
Publikováno v:
ICCAD
Interconnect spacing is getting increasingly smaller in advanced technology nodes, which adversely increases the capacitive coupling of adjacent interconnect wires. It makes crosstalk a significant contributor to signal integrity and timing, and it i
Publikováno v:
ITC
The globalization of IC manufacturing has increased the likelihood for IP providers to suffer financial and reputational loss from IP piracy. Logic locking prevents IP piracy by corrupting the functionality of an IP unless a correct secret key is ins
Publikováno v:
DAC
Latch clustering is a critical stage to reduce power consumption at cost of timing disruption during a modern SoC design flow. However, most existing latch clustering researches mitigate timing disruptions by indirectly minimizing latch displacement
Publikováno v:
ISPD
As the semiconductor process technology advances into sub-10nm regime, cell pin accessibility, which is a complex joint effect from the pin shape and nearby blockages, becomes a main cause for DRC violations. Therefore, a machine learning model for D