Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Geun-Soon Kang"'
Autor:
Kichan Park Kichan Park, Geun-Soon Kang, Bongsoon Kang, Myungjun Choi Myungjun Choi, Minkyu Son Minkyu Son, Seong-Won Kim
Publikováno v:
IEEE Transactions on Consumer Electronics. 42:285-289
In a digital camcorder system, an A/D converter which converts the analog CCD (charge coupled device) signal into digital codes has an important role in determining the system performance. An A/D converter which has an 8-bit resolution and a 40 MSPS
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2660263af1e90676f584fe6e870d4b52
https://doi.org/10.1109/30.536122
https://doi.org/10.1109/30.536122
Publikováno v:
AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360).
A calibration-free 3 V 12-bit 20 MSPS pipelined analog-to-digital (A/D) converter was implemented using 0.35 /spl mu/m CMOS technology. The proposed hybrid capacitor switching technique of two feedback capacitors is applied to improve the linearity w
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::401849e432d2a0592e6302f7a9bb64ba
https://doi.org/10.1109/apasic.1999.824060
https://doi.org/10.1109/apasic.1999.824060
Publikováno v:
1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.
A geometric-mean generator (A=/spl radic/(B/spl middot/C)) based on switched-current technique is proposed. A principle of superposition and cancellation is applied to the circuit. From the simulation results of the prototype circuit, it has an error
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::91f8a650b93e758e7e35ac8dd40106de
https://doi.org/10.1109/iscas.1996.539971
https://doi.org/10.1109/iscas.1996.539971
Publikováno v:
ICECS
Energy Economized Pass-transistor Logic (EEPL) is proposed. Adopting the principle of regenerative positive feedback with pMOS switches, we reduce the power in comparison with CPL and SRPL. To demonstrate the performance of EEPL, a low power 7-bit se
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f75ba3bed448ed590289092ea244aa38
https://doi.org/10.1109/icecs.1996.584563
https://doi.org/10.1109/icecs.1996.584563
Publikováno v:
ASP-DAC
This paper describes a single-chip solution for CMOS CCD camera interface systems. The required AGC gain in the proposed circuit is controlled directly by digital bits without conventional extra DAC's. Nonlinear errors such as offsets in signal paths
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a1c0a771320d85822cd9a245f05b3d16
https://doi.org/10.1109/aspdac.1999.759706
https://doi.org/10.1109/aspdac.1999.759706
Publikováno v:
AP-ASIC'99 First IEEE Asia Pacific Conference on ASICs (Cat No99EX360); 1999, p190-193, 4p
Publikováno v:
Proceedings of the ASP-DAC '99 Asia & South Pacific Design Automation Conference 1999 (Cat No99EX198); 1999, p45-45, 1p