Zobrazeno 1 - 10
of 20
pro vyhledávání: '"Geum-Jong Bae"'
Autor:
Jaehong Park, Taejung Lee, Woojin Rim, Geum-Jong Bae, Hoonki Kim, Taeyeong Kim, Jong-Hoon Jung, Dong-Won Kim, S. D. Kwon, Hakchul Jung, Hyung-Tae Kim, Taejoong Song, Soon-Moon Jung, Sanghoon Baek, Keun Hwi Cho, Jongwook Kye
Publikováno v:
ISSCC
Advanced technologies help to improve SRAM performance via recent transistor breakthroughs [1], which allow SRAM designers to focus on handling metal resistance by alleviating device performance impediments. Since SRAM margins are more vulnerable to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::39061cc23ae105d92382e833936d1627
https://doi.org/10.1109/isscc42613.2021.9365988
https://doi.org/10.1109/isscc42613.2021.9365988
Autor:
Mark S. Rodder, Mong-song Liang, Cheol Kim, Taek-Soo Jeon, Dong-Won Kim, Sunjung Kim, Kittl Jorge A, Jae Hoo Park, Wookje Kim, Jongwook Jeon, Sun-Ghil Lee, Myung-Geun Song, Kab-Jin Nam, Seung-Hun Lee, Yeon-Cheol Heo, Sean Lian, Sang-Woo Lee, Uihui Kwon, Geum-Jong Bae, Dong-il Bae, Kang-ill Seo, Krishna Kumar Bhuwalka, Ki-Hyun Hwang, Yihwan Kim, E. S. Jung, Jae-Young Park
Publikováno v:
2016 IEEE International Electron Devices Meeting (IEDM).
A novel tensile Si (tSi) and compressive SiGe (cSiGe) dual-channel FinFET CMOS co-integration scheme, aimed at logic applications for the 5nm technology node and beyond, is demonstrated for the first time, showing electrical performance benefits and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::10d564c76bd5f4f0442e06af3b149592
https://doi.org/10.1109/iedm.2016.7838496
https://doi.org/10.1109/iedm.2016.7838496
Autor:
Eun-ae Chung, Geum-Jong Bae, Nakanishi Toshiro, Maria Toledano-Luque, Jin-soak Kim, Guangfan Jiao, Thomas Kauerauf, Ki-Hyun Hwang, Dong-Won Kim, Seung-Hun Lee, Kab-Jin Nam, Dong-il Bae
Publikováno v:
2016 IEEE International Electron Devices Meeting (IEDM).
In this work, the oxide electric field (Eox) reduction caused by negatively charged traps is proposed to explain the robustness of SiGe pMOSFETs to negative gate bias temperature instability (NBTI) stress. The high density of negatively charged accep
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3c82966025039e6ec19c2953dd33bcc1
https://doi.org/10.1109/iedm.2016.7838518
https://doi.org/10.1109/iedm.2016.7838518
Autor:
Philip J. Oldiges, Hemanth Jagannathan, Kangguo Cheng, Christopher Prindle, C.-C. Yeh, R. Divakaruni, S. Kanakasabaphthy, Derrick Liu, Sean D. Burns, P. Montanini, T. Gow, Huiming Bu, Abhijeet Paul, Terry A. Spooner, Richard G. Southwick, Jin Cho, M. Celik, Mukesh Khare, Donald F. Canaperi, Young-Kwan Park, H. Mallela, Ravikumar Ramachandran, Bomsoo Kim, Dinesh Gupta, Balasubramanian S. Pranatharthi Haran, R. Kambhampati, M. Weybright, W. Yang, Vamsi Paruchuri, Tae-Chan Kim, R. Sampson, K. Kim, D. Chanemougame, John Iacoponi, Jay W. Strane, Ruilong Xie, D.I. Bae, Injo Ok, Matthew E. Colburn, T. Hook, Kang-ill Seo, Lars W. Liebmann, V. Sardesai, Hoon Kim, Neeraj Tripathi, H. Shang, M. Mottura, Reinaldo A. Vega, B. Hamieh, D. McHerron, Theodorus E. Standaert, Ju-Hwan Jung, S. Nam, E. Alptekin, Soon-Cheon Seo, Dechao Guo, J. G. Hong, Gen Tsutsui, Andreas Scholze, J. Jenq, Xiao Sun, Walter Kleemeier, James H. Stathis, Geum-Jong Bae
Publikováno v:
2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).
In this paper, we present a 10nm CMOS platform technology for low power and high performance applications with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2fdd9e37b1ad7ef1b69d8d55e103e9fa
https://doi.org/10.1109/icsict.2014.7021207
https://doi.org/10.1109/icsict.2014.7021207
Autor:
Jeffrey C. Shearer, Philip J. Oldiges, Soon-Cheon Seo, Terry A. Spooner, Matthew E. Colburn, Ravikumar Ramachandran, V. Sardesai, Kang-ill Seo, Dinesh Gupta, Richard G. Southwick, Xiao Sun, S. Stieg, H. Cai, S. Kanakasabaphthy, Vamsi Paruchuri, R. Sampson, Lars W. Liebmann, Walter Kleemeier, Kisik Choi, Deok-Hyung Lee, Christopher Prindle, R. Divakaruni, H. Shang, Abhijeet Paul, T. Gow, D. McHerron, Dechao Guo, Fee Li Lie, J. Nam, Neeraj Tripathi, Ruilong Xie, R. Kambhampati, Muthumanickam Sankarapandian, Balasubramanian S. Pranatharthi Haran, Carol Boye, James H. Stathis, B. Hamieh, John Iacoponi, Christopher J. Waskiewicz, Geum-Jong Bae, Derrick Liu, Sanjay Mehta, Reinaldo A. Vega, Terence B. Hook, Min Gyu Sung, Jay W. Strane, D.I. Bae, Robin Chao, Hoon Kim, F. Nelson, Theodorus E. Standaert, L. Jang, Erin Mclellan, M. Celik, S. Nam, Tae-Chan Kim, C.-C. Yeh, Sean D. Burns, P. Montanini, Charan V. V. S. Surisetty, Raghavasimhan Sreenivasan, Ju-Hwan Jung, B. Lherron, S.-B. Ko, E. Alptekin, Huiming Bu, Injo Ok, Jin Cho, Mukesh Khare, J. G. Hong, Gen Tsutsui, Andreas Scholze, Bomsoo Kim, D. Chanemougame, M. Mottura, M. Weybright, H. Mallela, K. Kim, Hemanth Jagannathan, Chanro Park, J. Jenq, Donald F. Canaperi, Young-Kwan Park, R. Jung, Kangguo Cheng
Publikováno v:
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.
A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d4d82166b734af3db83f196d83853ba5
https://doi.org/10.1109/vlsit.2014.6894342
https://doi.org/10.1109/vlsit.2014.6894342
Autor:
Sunae Seo, Nae-In Lee, Ki-chul Kim, Jin-Hee Kim, Geum-Jong Bae, Younseok Jeong, Chung-woo Kim, Myung-Yoon Um, Byoung-Jin Lee, Jae-woong Hyun, In-Wook Cho, Chae Hee-Soon
Publikováno v:
Japanese Journal of Applied Physics. 45:L998-L1000
Reliability studies of localized oxide–nitride–oxide memory (LONOM) devices are presented. The observed reduction in channel threshold voltage as a result of the retention charge loss of a programmed cell is demonstrated in terms of vertical leak
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::41a8d0d77e2ab8d5c15fe99cc07000c0
https://doi.org/10.1143/jjap.45.l998
https://doi.org/10.1143/jjap.45.l998
Autor:
Tetsuji Ueno, Lucia Feng, Ho-Kyu Kang, Geum-Jong Bae, J. Hautala, Hionsuck Baik, Yun Wang, Nae-In Lee, Ji Hye Yi, Hwa-Sung Rhee, W. Skinner, Seul-Gi Kim, Myung Sun Kim, Youngsu Chung, Hyunkyu Cho, Ho Lee
Publikováno v:
2006 International Workshop on Junction Technology.
High energy borane (B 2 H 6 ) gas cluster ion beam (GCIB) successfully enables a sub-10nm box-shaped dopant profile without channeling tail, and steep gradient (2.5nm/dec) in lateral direction. pFET using GCIB source/drain extension shows superior su
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5684eb907ca5f7e35803ae6f298faca2
https://doi.org/10.1109/iwjt.2006.1669444
https://doi.org/10.1109/iwjt.2006.1669444
Autor:
Hyun-Woo Lee, Tetsuji Ueno, Ho Lee, Heungsik Park, Cheol Kyu Lee, Hyunkyu Cho, Geum-Jong Bae, Hwa-Sung Rhee, Youn Hwa Jung, Nae-In Lee, Hion Suck Baik, Myung Sun Kim
Publikováno v:
2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..
This paper reports the first experimental demonstration of improved 1/f noise characteristics in a locally strained Si MOS through hydrogen-controlled stress liners and embedded SiGe (eSiGe). For NMOS, the high hydrogen density (1times1022cm-3) in th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::08f4c034dc52a318e94af7f286cd0f08
https://doi.org/10.1109/vlsit.2006.1705238
https://doi.org/10.1109/vlsit.2006.1705238
Autor:
K.C. Kim, Kwang Pyuk Suh, Nae-In Lee, S.T. Kang, Sun-Ghil Lee, Jung-hyeon Kim, Suk-pil Kim, I.S. Park, M.C. Kim, Seo Minwoong, H.-K. Kang, Geum-Jong Bae, I.W. Cho, Sei-jin Kim, Kwang-Ok Koh
Publikováno v:
2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).
A new Local SONOS structure has been proposed for an embedded NVM cell in 0.13 /spl mu/m standard CMOS logic process. The localized storage silicon nitride layer of Local SONOS cell provides the essential properties for the embedded NVM such as the c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::306aed91b1f4411ae059631ad62bfcfe
https://doi.org/10.1109/vlsit.2003.1221071
https://doi.org/10.1109/vlsit.2003.1221071
Autor:
Jung-hyeon Kim, S.D. Chae, C.W. Kim, S.A. Seo, Suk-pil Kim, Nae-In Lee, Hwang So-Hee, I.W. Cho, Geum-Jong Bae, Seung-Kwon Kim, B.R. Lim, M.C. Kim, B.J. Lee, H.-K. Kang, D.Y. Lee, K.C. Kim, Seo Minwoong, Sei-jin Kim, Kwang-Ok Koh
Publikováno v:
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..
We have successfully integrated 8M bits Localized ONO Memory (LONOM) for the embedded nonvolatile memory using 0.13um standard logic process with 5-level Cu metallization. which has a small cell size of 0.276UM and the simplest cell array structure.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::28c5dbefc441e2019896deee3319fc8a
https://doi.org/10.1109/vlsit.2004.1345502
https://doi.org/10.1109/vlsit.2004.1345502