Zobrazeno 1 - 10
of 10
pro vyhledávání: '"Gerolf Hoflehner"'
Publikováno v:
Electronic Notes in Theoretical Computer Science. 82:443-460
Like a processor executes flawlessly at different frequencies, a compiler should produce correct results at any optimization level. The Intel® Itanium® processor family with its new features, like the register stack engine and control- and data spe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::560c324116b8e2fca949d2ac148ccc7b
https://doi.org/10.1016/s1571-0661(05)82602-7
https://doi.org/10.1016/s1571-0661(05)82602-7
Publikováno v:
ACM SIGPLAN Notices. 37:117-128
Recently, a number of thread-based prefetching techniques have been proposed. These techniques aim at improving the latency of single-threaded applications by leveraging multithreading resources to perform memory prefetching via speculative prefetch
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::43f934d87ee9f60eb48bb9c86dd066df
https://doi.org/10.1145/543552.512544
https://doi.org/10.1145/543552.512544
Autor:
Jay Bharadwaj, W. Chuang, Kalyan Muthukumar, K. Menezes, Gerolf Hoflehner, J. Pierce, W.Y. Chen
Publikováno v:
IEEE Micro. 20:44-53
In planning the new EPIC (Explicitly Parallel Instruction Computing) architecture, Intel designers wanted to exploit the high level of instruction-level parallelism (ILP) found in application code. To accomplish this goal, they incorporated a powerfu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8efafcadd810802e30139741f263a4ae
https://doi.org/10.1109/40.877949
https://doi.org/10.1109/40.877949
Autor:
Ethan Schuchman, David R. Ditzel, Ronak Singhal, Guilherme Ottoni, Gautham N. Chinya, Jamison D. Collins, Gerolf Hoflehner, Amit Kumar, Hong Wang
Publikováno v:
Conf. Computing Frontiers
While the out-of-order engine has been the mainstream micro-architecture-design paradigm to achieve high performance, Transmeta took a different approach using dynamic binary translation (BT). To enable detailed comparison of these two radically diff
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::570f193d5118e75cc64bf96a2b6e4d08
https://doi.org/10.1145/2016604.2016629
https://doi.org/10.1145/2016604.2016629
Autor:
Gerolf Hoflehner
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783642119699
CC
CC
For predicated code a number of predicate analysis systems have been developed like PHG, PQA or PAS. In optimizing compilers for (fully) predicated architectures like the Itanium® 2 processor, the primary application for such systems is global regis
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a7d0f5034bbe982db429f58e568a905b
https://doi.org/10.1007/978-3-642-11970-5_11
https://doi.org/10.1007/978-3-642-11970-5_11
Autor:
Arun Kejariwal, Cameron B. Mcnairy, Daniel M. Lavery, Darshan Desai, Gerolf Hoflehner, Alexandru Nicolau, Alexander V. Veidenbaum
Publikováno v:
Computer Performance Evaluation and Benchmarking ISBN: 9783540937982
SPEC Benchmark Workshop
SPEC Benchmark Workshop
This paper presents the performance characteristics of the Intel®Itanium®2-based Montecito processor and compares its performance to the previous generation Madison processor. Measurements on both are done using the industry-standard SPEC CPU2006 b
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6939ef219180eb1346e825b9cb18bd95
https://doi.org/10.1007/978-3-540-93799-9_3
https://doi.org/10.1007/978-3-540-93799-9_3
Autor:
Alexandru Nicolau, Alexander V. Veidenbaum, Darshan Desai, Daniel M. Lavery, Gerolf Hoflehner, Arun Kejariwal
Publikováno v:
SIGMETRICS
Recently SPEC1 released the next generation of its CPU benchmark, widely used by compiler writers and architects for measuring processor performance. This calls for characterization of the applications in SPEC CPU2006 to guide the design of future mi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::39f6b1cb772d7476bb16046ef11fd1ce
https://doi.org/10.1145/1254882.1254930
https://doi.org/10.1145/1254882.1254930
Publikováno v:
MICRO
This paper discusses a repertoire of well-known and new compiler optimizations that help produce excellent server application performance and investigates their performance contributions. These optimizations combined produce a 40% speed-up in on-line
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::49aa06faca65461ae9b73ab96c78a1c1
https://doi.org/10.1109/micro.2004.11
https://doi.org/10.1109/micro.2004.11
Publikováno v:
International Symposium on Code Generation and Optimization, 2003. CGO 2003..
The Intel/spl reg/ Itanium/spl reg/ architecture contains a number of innovative compiler-controllable features designed to exploit instruction level parallelism. New code generation and optimization techniques are critical to the application of thes
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::373acaeeb06c1e01618632e321b5efc6
https://doi.org/10.1109/cgo.2003.1191538
https://doi.org/10.1109/cgo.2003.1191538
Autor:
Daniel M. Lavery, Perry Wang, John Paul Shen, Gerolf Hoflehner, Steve Shih-wei Liao, Hong Wang
Publikováno v:
PLDI
Recently, a number of thread-based prefetching techniques have been proposed. These techniques aim at improving the latency of single-threaded applications by leveraging multithreading resources to perform memory prefetching via speculative prefetch
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5f515fc29f79f83683504983e2d44a00
https://doi.org/10.1145/512529.512544
https://doi.org/10.1145/512529.512544