Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Gerhard Mitteregger"'
Autor:
Christian Ebner, Ernesto Romani, Gerhard Mitteregger, T. Blon, Christophe Holuigue, Stephan Mechnig
Publikováno v:
IEEE Journal of Solid-State Circuits. 41:2641-2649
A wide bandwidth continuous-time sigma-delta ADC, operating between 20 and 40 MS/s output data rate, is implemented in 130-nm CMOS. The circuit is targeted for applications that demand high bandwidth, high resolution, and low power, such as wireless
Autor:
H. Geib, Ernesto Romani, M. Moyal, T. Blon, M. Vena, A. Melodia, G.L.G. de Mercey, Gerhard Mitteregger, Christian Ebner, H. Werker, Stephan Mechnig, Christophe Holuigue, F. Roger, J. Fisher
Publikováno v:
IEEE Journal of Solid-State Circuits. 39:2349-2358
A 4:1 SERDES IC suitable for SONET OC-192 and 10-Gb/s Ethernet is presented. The receiver, which consists of a limiting amplifier, a clock and data recovery unit, and a demultiplexer, locks automatically to all data rates in the range 9.95-10.7 Gb/s.
Autor:
Gerhard Mitteregger, Brian Brandt
Publikováno v:
2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).
Analog-to-digital converters for wireless systems continue to improve in noise and distortion performance, sample rate, and integration. This steady advance allows them to move closer to the antenna and digitize an increasing number of communication
Autor:
Brian Brandt, Gerhard Mitteregger
Publikováno v:
ISSCC
Autor:
Christophe Holuigue, T. Blon, A. Melodia, Gerhard Mitteregger, Stephan Mechnig, V. Melini, Ernesto Romani, Christian Ebner
Publikováno v:
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.
A 3rd-order single-loop CT DeltaSigma modulator with a 4b internal quantizer operating at 640MHz achieves 76dB SNR, -78dB THD, and 74dB SINAD in a 20MHz signal bandwidth with an OSR of 16. The modulator operates between 20 to 40MS/S output data rate