Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Gerald S. Leatherman"'
Autor:
Benjamin J. Orr, Nathan Jack, C. Auth, A. Schmitz, Tony Acosta, Steven S. Poon, Che-Yun Lin, Abdur Rahman, C. AnDyke, Rahim Kasim, K. Downes, G. McPherson, Sunny Chugh, Madhavan Atul, D. Nminibapiel, Adam Neale, K. Sethi, Seung Hwan Lee, S. Ramey, Tanmoy Pramanik, Michael L. Hattendorf, Emre Armagan, J. Palmer, Subhash M. Joshi, Ian R. Post, C. M. Pelto, P. Nayak, Yeoh Andrew W, G. Martin, Gerald S. Leatherman, H. Wu, N. Seifert, A. Lowrie, R. Grover, H. Mao
Publikováno v:
IRPS
We provide a comprehensive overview of the reliability characteristics of Intel’s 10+ logic technology. This is a 10 nm technology featuring the third generation of Intel’s FinFETs, seventh generation of strained silicon, fifth generation of high
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::76e7a8286d09b3f3bfcb1c27f6a51e61
https://doi.org/10.1109/irps45951.2020.9128345
https://doi.org/10.1109/irps45951.2020.9128345
Autor:
Yeoh Andrew W, W. Han, Manvi Sharma, J. Shin, I. Post, M. Tanniru, T. Mule, Madhavan Atul, Gerald S. Leatherman, Kevin J. Fischer, Y-H. Wu, M. Sprinkle, Prasun Sinha, S. Anand, J. Steigerwald, S. Nigam, V. Souw, C. Ganpule, M. Asoro, Haran Mohit K, K-S. Lee, C. Pelto, P. Yashar, S. Samarajeewa, M. Mori, A. Tripathi, S. Kirby, C. Auth, M. Aykol, H. Hiramatsu, K. Marla, H. Jeedigunta, V. Chikarmane, M. Buehler, Nicholas J. Kybert
Publikováno v:
2018 IEEE International Interconnect Technology Conference (IITC).
This paper describes Intel's 10nm highperformance logic technology interconnect stack featuring 13 metal layers comprising two self-aligned quad patterned and four self-aligned double patterned layers. Quad patterned interconnect layers are introduce
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0fa7cc3fb3c8d31dc8c2da50fdf17147
https://doi.org/10.1109/iitc.2018.8430489
https://doi.org/10.1109/iitc.2018.8430489
Autor:
Rahim Kasim, J. Palmer, A. Schmitz, I. Tsameret, F. Pan, C. Auth, Flavio Griggio, Yeoh Andrew W, Gerald S. Leatherman, Joseph M. Steigerwald, J. Hicks, J. Shin, A. Madhavan, N. Toledo
Publikováno v:
IRPS
This paper discusses the reliability of a new metallization scheme for 10nm back end of line (BEOL) local interconnect. Electromigration (EM) and time dependent dielectric breakdown (TDDB) on cobalt fill interconnects are investigated. Significant in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::58d63251175c58f96eca878418f6167f
https://doi.org/10.1109/irps.2018.8353641
https://doi.org/10.1109/irps.2018.8353641
Publikováno v:
IRPS
Development of an industry leading 10nm CMOS process technology with the highest reported drive currents and cell densities involved numerous enabling innovations, judicious choice of design rules, novel features, and most importantly a relentless pu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::288c932b80e0017afbc7a6f13a86692d
https://doi.org/10.1109/irps.2018.8353648
https://doi.org/10.1109/irps.2018.8353648
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 13:350-356
Shifts in transistor performance due to mechanical stress resulting from interaction of die, packaging, test socketing, and board mount are discussed. Mechanical-stress-induced transistor drive current shifts are measured indirectly using ring oscill
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::851d5c9315ad0a33c33577d397d31acb
https://doi.org/10.1109/tdmr.2013.2261817
https://doi.org/10.1109/tdmr.2013.2261817
Autor:
Md. Enamul Kabir, Dave W. Young, Carl Sapp, Bahattin Kilic, Ioan Sauciuc, Gerald S. Leatherman
Publikováno v:
IRPS
Integrated Circuits continuously scale including die thicknesses to achieve lower total z-height. As has been previously reported, die thinning can impact transistor performance due to mechanical stresses generated by the package. This paper is inves
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1df2747329bccb060355241c4c5a8ec4
https://doi.org/10.1109/irps.2015.7112754
https://doi.org/10.1109/irps.2015.7112754
Publikováno v:
2012 IEEE International Reliability Physics Symposium (IRPS).
Shifts in transistor performance due to mechanical stress resulting from interaction of die, packaging, test socketing, and board mount are discussed. Mechanical stress induced transistor drive current shifts are measured indirectly using ring oscill
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::20456c5e6d84a02381e84f014d195d7c
https://doi.org/10.1109/irps.2012.6241791
https://doi.org/10.1109/irps.2012.6241791