Zobrazeno 1 - 4
of 4
pro vyhledávání: '"George Stojakovic"'
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 26:442-447
Bevel etch used during wafer fabrication for semiconductor devices is discussed. In this case, the bevel etch process was utilized in middle of the line processing (MOL) to reduce back end of line (BEOL) defectivity. Tungsten and titanium nitride fil
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::b6e14a0cc03cc9ae02f99efa8a649566
https://doi.org/10.1109/tsm.2013.2283080
https://doi.org/10.1109/tsm.2013.2283080
Autor:
Michael Goss, Hiroaki Takikawa, Min-Joon Park, Chih-Ming Sun, Jun Belen, Mark Kelling, Lin Pinyen, James Paris, Lucy Chen, George Stojakovic, Troy S. Detrick, Yii-Cheng Lin, Shannon Dunn, Wenli Collison, Norman Fish
Publikováno v:
SPIE Proceedings.
In the Global 450mm Equipment Development Consortium (G450C), a 193i guided directed self-assembly (DSA) pattern has been used to create structures at the 14nm node and below. The first guided DSA patterned wafer was ready for etch process developmen
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c0d8e98e060f2cfd4a3053891458b1c3
https://doi.org/10.1117/12.2218537
https://doi.org/10.1117/12.2218537
Autor:
George Stojakovic, Shoaib Hasan Zaidi, Peter A. Rosenthal, Cornel Bozdog, Alois Gutmann, Sylvie Charpenay, Ulrich Mantz
Publikováno v:
SPIE Proceedings.
A method that uses Fourier Transform Infrared (FTIR) Reflectance spectroscopy to determine the depths of poly silicon filled trenches is described. These trenches, which form the cells for trench DRAM, are arranged in arrays that are periodic in both
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cf4ecc97f57fd8c8f8b37afca5eb190b
https://doi.org/10.1117/12.484998
https://doi.org/10.1117/12.484998
Autor:
Yasuyuku Taniguchi, Ulrich Egger, Gerhard Beitel, Kazuhiro Tomioka, Shigeki Sugimoto, Hiroyuki Kanaya, George Stojakovic, Rainer Bruchhaus, Haoren Zhuang
Publikováno v:
MRS Proceedings. 748
A 32 Mbit chain FeRAM™ stack with 0.20μm minimum feature size was etched with two subsequent lithography/RIE steps: in mask step 1 the platinum/SRO (strontium ruthenium oxide) top electrode and the PZT (lead zirconate titanate) layer, in mask step
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dd2d71b2c1e5209b167e063a36979531
https://doi.org/10.1557/proc-748-u1.7
https://doi.org/10.1557/proc-748-u1.7