Zobrazeno 1 - 6
of 6
pro vyhledávání: '"George Sobral Silveira"'
Publikováno v:
International Journal of Reconfigurable Computing, Vol 2012 (2012)
Power gating is one of the most efficient power consumption reduction techniques. However, when applied in several different parts of a complex design, functional verification becomes a challenge. Lately, the verification process of this technique ha
Externí odkaz:
https://doaj.org/article/33749b0a79d9469fbe6d7e62a39fe9d3
Publikováno v:
Revista Eletrônica de Iniciação Científica em Computação; v. 18, n. 1 (2020): Revista Eletrônica de Iniciação Científica em Computação
Com os avanços tecnológicos e a integração de diversos sistemas de segurança, é possível evitar, por exemplo, que uma pessoa acesse determinado ambiente sem autorização. Devido ao grande aumento da circulação de pessoas no IFPB Campus Camp
Publikováno v:
International Journal of Reconfigurable Computing, Vol 2012 (2012)
Power gating is one of the most efficient power consumption reduction techniques. However, when applied in several different parts of a complex design, functional verification becomes a challenge. Lately, the verification process of this technique ha
Publikováno v:
Dynamic Modelling
In the present day, partial reconfiguration is a reality (Becker & Hartenstein, 2003). There are many industries investing as well in fine-grain (like FPGAs (Huebner et al., 2004)) as in coarse grain solutions (eg. XPP (Becker & Vorbach, 2003)). This
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::84300e337896eeeb15989ee0e84f0bc5
https://doi.org/10.5772/7094
https://doi.org/10.5772/7094
Publikováno v:
SBCCI
With the growth of number of transistors, thermal density and market drive towards battery power, the necessity to develop low power integrated circuits is evident. There are several methodologies and techniques that help in the development of this t
Publikováno v:
SBCCI
The advent of the new VLSI technology and SoC design methodologies has brought about an explosive growth to the complexity of modern electronic circuits. As a result, functional verification has become a major bottleneck in any digital design flow. F