Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Geoffrey Choh-Fei Yeap"'
Autor:
Khaled Ahmed, Ming-Ren Lin, David Bang, Geoffrey Choh-Fei Yeap, Miryeong Song, Qi Xiang, Effiong Ibok
Publikováno v:
1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).
Summary form only given. In this paper, we report the performance and reliability of sub-100 nm MOSFETs with ultra thin direct tunneling (DT) gate oxides. Both pure oxides and nitrided oxides down to 17 /spl Aring/ were investigated. For a L/sub g/ o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d72ea41c3e1daea76d207a5f3c42ee36
https://doi.org/10.1109/vlsit.1998.689240
https://doi.org/10.1109/vlsit.1998.689240
Autor:
Geoffrey Choh-Fei Yeap, Effiong Ibok, Miryeong Song, Khaled Ahmed, Ming-Ren Lin, Qi Xiang, David Bang
Publikováno v:
56th Annual Device Research Conference Digest (Cat. No.98TH8373).
Performance and reliability of sub-100 nm gate length devices using a dual gate and shallow trench isolated CMOS technology were investigated. Ultra-thin direct tunneling (DT) thermal, nitrous and nitric oxides as thin as 1.3 nm are used. Only N-MOS
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::baa4bb0b556d79d31dd8f63d69019ba7
https://doi.org/10.1109/drc.1998.731099
https://doi.org/10.1109/drc.1998.731099
Publikováno v:
1998 3rd International Symposium on Plasma Process-Induced Damage (Cat. No.98EX100).
The effect of using a Cu damascene process on plasma process-induced damage (PPID) is studied in relationship to future scaling rules. Wafers processed using a Cu damascene metallization scheme show little increase in gate leakage as antenna ratios a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1229668e846b43ef9b9112b660c29bac
https://doi.org/10.1109/ppid.1998.725575
https://doi.org/10.1109/ppid.1998.725575
Publikováno v:
SPIE Proceedings.
Device degradation due to hot-carrier injection in sub-100 nm gate length devices has been investigated. 90 nm gate length (CD SEM) N-MOSFETs with 2.2 nm nitrous oxide (Idsat equals 735 uA/micrometer, Idoff equals 1.1 nA/micrometer Vdd equals 1.5 V)
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::536d72f40309e77e45e0d92f45c39243
https://doi.org/10.1117/12.323979
https://doi.org/10.1117/12.323979
Autor:
Christopher A. Spence, Geoffrey Choh-Fei Yeap, Ming-Ren Lin, Subash Gupta, Bhanwar Singh, Qi Xiang
Publikováno v:
SPIE Proceedings.
This paper reports experimental results of polysilicon gate patterning for sub-100 nm and deep sub-100 nm (less than 50 nm) MOS technology development. Sub-100 nm and deep sub-100 nm polysilicon gates have been achieved using an aggressive etch bias
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::48c4383c9875e264791c8ea8366976ac
https://doi.org/10.1117/12.323977
https://doi.org/10.1117/12.323977
Publikováno v:
SPIE Proceedings.
Gate insulator/stack scaling is arguably one of the most challenging aspects of device scaling. As gate lengths are scaled into the sub-100 nm regime, alternate materials other than SiO2 will be needed to continue device scaling. The SIA roadmap has
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a0ef97e7526bcb652da4a716f8da85f6
https://doi.org/10.1117/12.323991
https://doi.org/10.1117/12.323991
Publikováno v:
Electronics Letters. 34:1150
Fringing-induced barrier lowering (FIBL), a new anomalous degradation in device turn-off/on characteristics in sub-100 nm devices with high-K gate dielectrics, is reported. FIBL is clearly evident for K>25 and worsens as K increases (without buffer o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9d752022b2dd60e9d21bc2aa01e34947
https://doi.org/10.1049/el:19980800
https://doi.org/10.1049/el:19980800