Reusable System-level Power-aware IP Modeling Approach

Autor: Genov, Antonio, Verdier, François, Leconte, Loic

Publikováno v: Design and Verification DVCon U.S. 2022
Design and Verification DVCon U.S. 2022, accellera, Feb 2022, conférence virtuelle (initialement prévue à San Jose), United States. pp.10

International audience; In many areas of the semiconductor industry, System-on Chip (SoC) power analysis and management is a critical process for maintaining low-power profiles. Due to the complexity of modern SoC designs and the definition of their

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::ebf6fa9f55256a9694443a221c7c3d61
https://hal.archives-ouvertes.fr/hal-03454118

Timing-Aware high level power estimation of industrial interconnect module

Autor: Ben Ameur, Amal, Genov, Antonio, Verdier, François, Leconte, Loic

Publikováno v: Design and Verification Conference and Exhibition" (DVCON)
Design and Verification Conference and Exhibition" (DVCON), Oct 2020, conférence virtuelle, France

International audience; The semiconductor industry is developing smaller transistors and succeeding in increasing their on-chip integration density. Therefore, the computing power of modern Integrated Circuits (IC) is constantly increasing and their

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::5908a7a90f782b8ceda3d9453be73547
https://hal.archives-ouvertes.fr/hal-02951763