Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Gautham N. Chinya"'
Autor:
Hong Fremont Wang, Vivek De, Subramaniam Maiyuran, Pascal Meinerzhagen, Sriram R. Vangal, Vaibhav Vaidya, Krishnan Ravichandran, George E. Matthew, Brando Perez Esparza, Gautham N. Chinya, M. Woodman, Stephen Kim, Luis Cuellar, Somnath Paul, Minki Cho, Xiang Zou, Bala Iyer, Deepak A. Mathaikutty, Carlos Tokunaga, Joseph F. Ryan, Charles Augustine, James W. Tschanz, Andres Malavasi, Ashwin Mendon, Muhammad M. Khellah, Rinkle Jain, Chung-Ching Peng, Jaydeep P. Kulkarni, Yuyun Liao
Publikováno v:
IEEE Journal of Solid-State Circuits. 54:144-157
Graphics workloads make highly dynamic use of resources such as execution units (EUs), and thus can benefit from fast, fine-grain dynamic voltage and frequency scaling (DVFS) and retentive sleep. This paper presents a 14-nm graphics processing unit (
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2a4358083f5cadb7a92dbf4868088c82
https://doi.org/10.1109/jssc.2018.2875097
https://doi.org/10.1109/jssc.2018.2875097
Autor:
Deepak A. Mathaikutty, Gautham N. Chinya, Kim Sang Kyun, Cormac Brick, Debabrata Mohapatra, Arnab Raha, Raymond Sung, Guruguhanathan Venkataramanan
Publikováno v:
VLSI Design
AI acceleration is one of the most actively researched fields in IP and system design. The introduction of specialized AI accelerators in the cloud and at the edge has made it possible to deploy large scaled AI solutions that automate tasks that were
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bb6c1ecd27992c0f5fcbef9ba489a576
https://doi.org/10.1109/vlsid51830.2021.00061
https://doi.org/10.1109/vlsid51830.2021.00061
Autor:
Andrew Lines, Chit-Kwan Lin, Georgios D. Dimou, Tsung-Han Lin, Nabil Imam, Ruokun Liu, Cao Yongqiang, Gautham N. Chinya, Andreas Wild, Hong Wang, Prasad Joshi, Jonathan Tse, Yoon Seok Yang, Steven McCoy, Sri Harsha Choday, Arnab Paul, Michael Davies, Yuyun Liao, Guruguhanathan Venkataramanan, Yi-Hsin Weng, Deepak A. Mathaikutty, Shweta Jain, Narayan Srinivasa
Publikováno v:
IEEE Micro. 38:82-99
Loihi is a 60-mm2 chip fabricated in Intels 14-nm process that advances the state-of-the-art modeling of spiking neural networks in silicon. It integrates a wide range of novel features for the field, such as hierarchical connectivity, dendritic comp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1d26cda1c55b4debd0e89fd1b92ddbb9
https://doi.org/10.1109/mm.2018.112130359
https://doi.org/10.1109/mm.2018.112130359
Autor:
Stephen J. Tarsa, Chit-Kwan Lin, Karthik Sankaranarayanan, Ronak Singhal, Julien Sebot, Gautham N. Chinya, Rangeen Basu Roy Chowdhury, Hong Wang, Jayesh Gaur, Robert S. Chappell
Publikováno v:
ISCA
Processors that adapt architecture to workloads at runtime promise compelling performance per watt (PPW) gains, offering one way to mitigate diminishing returns from pipeline scaling. State-of-the-art adaptive CPUs deploy machine learning (ML) models
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c148f47b55dcdd9d29742a4cb417169b
https://doi.org/10.1145/3307650.3322267
https://doi.org/10.1145/3307650.3322267
Publikováno v:
PLDI
We present a compiler for Loihi, a novel manycore neuromorphic processor that features a programmable, on-chip learning engine for training and executing spiking neural networks (SNNs). An SNN is distinguished from other neural networks in that (1) i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3959e35b5bf66ec1d06bb70c0f5b47a2
https://doi.org/10.1145/3192366.3192371
https://doi.org/10.1145/3192366.3192371
Autor:
Bala Iyer, Ashwin Mendon, Pascal Meinerzhagen, Vaibhav Vaidya, Jaydeep P. Kulkarni, Muhammad M. Khellah, Brando Perez Esparza, Somnath Paul, Minki Cho, Sriram R. Vangal, Subramaniam Maiyuran, Rinkle Jain, Yuyun Liao, George E. Matthew, Deepak A. Mathaikutty, Vivek De, Hong Wang, Gautham N. Chinya, Chung-Ching Peng, Carlos Tokunaga, Joseph F. Ryan, Stephen Kim, Charles Augustine, Chris Zou, Michael Woodman, Krishnan Ravichandran, James W. Tschanz, Andres Malavasi, Luis Cuellar
Publikováno v:
ISSCC
Graphics workloads are highly dynamic in nature, using multi-threaded SIMD execution units (EUs), fixed-function units, samplers, and media accelerators to provide ever-increasing amounts of graphics performance. These workloads are often limited by
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::971a260202a052615da47efb1ee89e79
https://doi.org/10.1109/isscc.2018.8310172
https://doi.org/10.1109/isscc.2018.8310172
Autor:
Jamison D. Collins, Hong Jiang, Hong Wang, Perry Wang, Thomas A. Piazza, Gautham N. Chinya, Guei-Yuan Lueh
Publikováno v:
ACM SIGOPS Operating Systems Review. 45:11-20
In this paper, we introduce Bothnia, an extension to the Intel production graphics driver to support a shared virtual memory heterogeneous multithreading programming model. With Bothnia, the Intel graphics device driver can support both the tradition
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fbd3a803a441a524b80794065b43f793
https://doi.org/10.1145/1945023.1945027
https://doi.org/10.1145/1945023.1945027
Autor:
Hong Jiang, Gautham N. Chinya, Guei-Yuan Lueh, Jamison D. Collins, Nick Y. Yang, Hong Wang, Perry Wang, Xinmin Tian, Milind B. Girkar
Publikováno v:
PLDI
Future mainstream microprocessors will likely integrate specialized accelerators, such as GPUs, onto a single die to achieve better performance and power efficiency. However, it remains a keen challenge to program such a heterogeneous multicore platf
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2d4b69beaff91379f341c5e63bb7b98e
https://doi.org/10.1145/1273442.1250753
https://doi.org/10.1145/1273442.1250753
Autor:
John Paul Shen, Gautham N. Chinya, Perry Wang, Ryan Rakvic, Richard A. Hankins, Hong Wang, Jamison D. Collins
Publikováno v:
ISCA
Microprocessor design is undergoing a major paradigm shift towards multi-core designs, in anticipation that future performance gains will come from exploiting threadlevel parallelism in the software. To support this trend, we present a novel processo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3468d84d4420dfe37420fd4ea888cdf6
https://doi.org/10.1145/1150019.1136495
https://doi.org/10.1145/1150019.1136495
Autor:
Ethan Schuchman, David R. Ditzel, Ronak Singhal, Guilherme Ottoni, Gautham N. Chinya, Jamison D. Collins, Gerolf Hoflehner, Amit Kumar, Hong Wang
Publikováno v:
Conf. Computing Frontiers
While the out-of-order engine has been the mainstream micro-architecture-design paradigm to achieve high performance, Transmeta took a different approach using dynamic binary translation (BT). To enable detailed comparison of these two radically diff
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::570f193d5118e75cc64bf96a2b6e4d08
https://doi.org/10.1145/2016604.2016629
https://doi.org/10.1145/2016604.2016629