Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Gaurav Rajavendra Reddy"'
Autor:
Gaurav Rajavendra Reddy, Kostas Adam
Publikováno v:
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design.
Autor:
Gaurav Rajavendra Reddy, Jingxian Tian, Carl Sechen, William Swartz, Yiorgos Makris, Mustafa M. Shihab, Bharath Ramanidharan
Publikováno v:
ISCAS
A recently proposed TRAnsistor-level Programmable (TRAP) fabric can enable seamless on-die integration of high-density reconfigurable logic with custom ICs. However, state-of-the-art CAD tools are developed for either ASICs or FPGAs and do not suppor
Autor:
Carl Sechen, Yiorgos Makris, Jingxian Tian, Bharath Ramanidharan, Gaurav Rajavendra Reddy, Suraag Sunil Tellakula, Mustafa M. Shihab
Publikováno v:
VTS
A recently introduced TRAnsistor-level Programmable fabric (TRAP) has demonstrated great promise towards seamless unification of high-density reconfigurable logic with Application-Specific Integrated Circuits (ASICs). However, practical deployment of
Continuous technology scaling and the introduction of advanced technology nodes in Integrated Circuit (IC) fabrication is constantly exposing new manufacturability issues. One such issue, stemming from complex interaction between design and process,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::839e2d46e1ec2744702bbef5f5b789f1
Autor:
Siddharth Garg, Gaurav Rajavendra Reddy, Benjamin Tan, Kang Liu, Ramesh Karri, Yiorgos Makris
Deep learning (DL) offers potential improvements throughout the CAD tool-flow, one promising application being lithographic hotspot detection. However, DL techniques have been shown to be especially vulnerable to inference and training time adversari
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f6c8c73b5dd0e21032913adc36f9e543
Publikováno v:
MTV
Advanced technology nodes suffer from high systematic defectivity. A significant part of such defectivity is caused by Lithographic Hotspots. Hotspots are Design Rule Check (DRC) clean areas of a layout which tend to show abnormal variation due to co
Publikováno v:
ITC
Contemporary technology nodes exhibit high defectivity due to complex interactions between the process and certain layout topologies/patterns. Foundries identify such patterns during diagnosis, Scanning Electron Microscope (SEM) inspections, Failure
Publikováno v:
ICCAD
Extensive technology scaling has not only increased the complexity of Integrated Circuit (IC) fabrication but also multiplied the challenges in the Design For Manufacturability (DFM) space. Among these challenges, detection of design weak-points, pop
Autor:
Mustafa M. Shihab, Jingxiang Tian, William Swartz, Bo Hu, Carl Sechen, Yiorgos Makris, Benjamin Carrion Schaefer, Gaurav Rajavendra Reddy
Publikováno v:
ACM Great Lakes Symposium on VLSI
The protection of Intellectual Property (IP) has emerged as one of the most serious areas of concern in the semiconductor industry. To address this issue, we present a method and architecture to map selective portions of a design, given as a behavior
Autor:
William Swartz, Carl Sechen, Yiorgos Makris, Benjamin Carrion Schaefer, Gaurav Rajavendra Reddy, Jingxiang Tian, Mustafa M. Shihab, Bo Hu
Publikováno v:
DATE
Widespread adoption of the fabless business model and utilization of third-party foundries have increased the exposure of sensitive designs to security threats such as intellectual property (IP) theft and integrated circuit (IC) counterfeiting. As a