Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Ganglong Li"'
Publikováno v:
Journal of Materials Research and Technology, Vol 22, Iss , Pp 1449-1461 (2023)
Experimental fracture mechanics at the microscale became an indispensable tool for understanding and analyzing the solder joint degradation in microelectronics packaging, which is facing severe temperature swings and is prone to failure due to the de
Externí odkaz:
https://doaj.org/article/8ccb0184509644b3adf537acbb7505d9
Publikováno v:
Micromachines, Vol 14, Iss 10, p 1953 (2023)
The era of 20 nm integrated circuits has arrived. There exist abundant heterogeneous micro/nano structures, with thicknesses ranging from hundreds of nanometers to sub-microns in the IC back end of the line stack, which put stringent demands on the r
Externí odkaz:
https://doaj.org/article/aec6f7295ed64fff9d58814899309278
Publikováno v:
Nanomaterials, Vol 12, Iss 10, p 1699 (2022)
Microvia interconnectors are a critical element of 3D packaging technology, as they provide the shortest interconnection path between stacked chips. However, low efficiency of microvia filling is a long-standing problem. This study proposed a two-ste
Externí odkaz:
https://doaj.org/article/6674674b71a2494eb1abb8de416026a2
Publikováno v:
AIP Advances, Vol 7, Iss 9, Pp 095320-095320-10 (2017)
Three-dimensional (3D) integration technology using Cu interconnections has emerged as a promising solution to improve the performance of silicon microelectronic devices. However, Cu diffuses into SiO2 and requires a barrier layer such as Ta to ensur
Externí odkaz:
https://doaj.org/article/7fa8dd3f0c064032a7a66896711b2aed
Publikováno v:
2020 21st International Conference on Electronic Packaging Technology (ICEPT).
With the further shrinking of chip feature size, Thermocompression bonding (TCB) is widely used in ultra-fine pitch flip welding products. Therefore, research and master important process parameters such as temperature, time and force are crucial to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::951191e13665ed598bb3b5f404a23ebb
https://doi.org/10.1109/icept50128.2020.9202998
https://doi.org/10.1109/icept50128.2020.9202998
High-performance ultra-low-k fluorine-doped nanoporous organosilica films for inter-layer dielectric
Autor:
Zhuo Chen, Lei Shi, Junhui Li, Ganglong Li, Andrew A. O. Tay, Liancheng Wang, Guang Zheng, Zijun Ding, Wenhui Zhu
Publikováno v:
Journal of Materials Science. 54:2379-2391
Development of low-k materials is critical for further improving the performance of integrated circuits. In this work, a novel type of fluorine-doped ultra-low-k porous SiCOH films has been produced. The chemical composition and bond configurations o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::995373e8df661039c35c635440b69de5
https://doi.org/10.1007/s10853-018-3013-x
https://doi.org/10.1007/s10853-018-3013-x
Publikováno v:
Journal of Materials Science. 53:7809-7821
Phase relations in Cu–Ti–Hf ternary system have been studied by diffusion triple technique supplemented with typical alloy sampling method. Based on results from electron-probe microscopy analysis and X-ray diffraction, isothermal sections of the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2089367280dac9630c4e4e6582d9f6f2
https://doi.org/10.1007/s10853-018-2058-1
https://doi.org/10.1007/s10853-018-2058-1
Publikováno v:
2017 18th International Conference on Electronic Packaging Technology (ICEPT).
Integrated circuits (ICs) undergo dimensional reduction and the functional unit of density dramatically increases, the reliability issue becomes more critical, especially with respect to three-dimensional (3D) silicon integration technology. Through-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d3da65969965c8c29ee8720955164017
https://doi.org/10.1109/icept.2017.8046687
https://doi.org/10.1109/icept.2017.8046687
Publikováno v:
2017 18th International Conference on Electronic Packaging Technology (ICEPT).
In this paper, a chip level stacked module, 100-µm pitch chip on chip (CoC) interconnection with Cu/Sn/Cu microbumps, was assembled by thermal compression bonding process. Daisy chain circuit in the package is electrically connected to high speed Da
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aa97440051b0cbae1647a15046ba9564
https://doi.org/10.1109/icept.2017.8046692
https://doi.org/10.1109/icept.2017.8046692
Publikováno v:
2016 17th International Conference on Electronic Packaging Technology (ICEPT).
Through Silicon Via(TSVs) technology is one of the most prominent feature in future microelectronic devices packaging. Since TSVs contain the interfaces of heterogeneous materials that have high CTE mismatch, and would hence produce large thermal str
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f3f38a19658c5c15d7c3925b2507033f
https://doi.org/10.1109/icept.2016.7583372
https://doi.org/10.1109/icept.2016.7583372