Zobrazeno 1 - 10
of 30
pro vyhledávání: '"Ganapathy, Shrikanth"'
Autor:
Kokolis, Apostolos, Mantri, Namrata, Ganapathy, Shrikanth, Torrellas, Josep, Kalamatianos, John
The increased memory demands of workloads is putting high pressure on Last Level Caches (LLCs). Unfortunately, there is limited opportunity to increase the capacity of LLCs due to the area and power requirements of the underlying SRAM technology. Int
Externí odkaz:
http://arxiv.org/abs/2112.10632
Autor:
Ganapathy, Shrikanth
Publikováno v:
TDX (Tesis Doctorals en Xarxa).
In this thesis, we have investigated the impact of parametric variations on the behaviour of one performance-critical processor structure - embedded memories. As variations manifest as a spread in power and performance, as a first step, we propose a
Externí odkaz:
http://hdl.handle.net/10803/144560
Publikováno v:
In Integration, the VLSI Journal June 2012 45(3):246-252
Branch prediction units are key performance components in modern microprocessors as they are widely used to address control hazards and minimize misprediction stalls. The continuous urge of high performance has led designers to integrate highly sophi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=od______2127::cd2717f2683e3f968a8699bfa14517f3
https://pergamos.lib.uoa.gr/uoa/dl/object/uoadl:3183036
https://pergamos.lib.uoa.gr/uoa/dl/object/uoadl:3183036
Branch predictors are widely used to boost the performance of microprocessors. However, this comes at the expense of power because accurate branch prediction requires simultaneous access to several large tables on every fetch. Consumed power can be d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=od______2127::bd9f2cfedac1b7ccee56c60f4ce7ca46
https://pergamos.lib.uoa.gr/uoa/dl/object/uoadl:3177654
https://pergamos.lib.uoa.gr/uoa/dl/object/uoadl:3177654
Publikováno v:
DAC: Annual ACM/IEEE Design Automation Conference; 2017, Issue 54, p613-618, 6p
Autor:
Ganapathy, Shrikanth, Canal Corretger, Ramon, González Colás, Antonio María, Rubio Sola, Jose Antonio
Publikováno v:
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
instname
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
instname
In this paper, we present an on-die post-silicon binning methodology that takes into account the effect of static and dynamic variations and categorizes every processor based on power/performance.The proposed scheme is composed of a discretization ha
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::a4aef24baed8cee22aecce412454f5dd
http://hdl.handle.net/2117/13911
http://hdl.handle.net/2117/13911
Autor:
Ganapathy, Shrikanth, Canal Corretger, Ramon, González Colás, Antonio María, Rubio Sola, Jose Antonio
Publikováno v:
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
instname
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
instname
Estimation of static and dynamic energy of caches is critical for high-performance low-power designs. Commercial CAD tools performing energy estimation statically are not aware of the changing operating and environmental conditions which makes the pr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::1a5e68a89b958c657d96829cb68b86a4
http://hdl.handle.net/2117/24024
http://hdl.handle.net/2117/24024
Publikováno v:
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE); 2016, p838-841, 4p
Publikováno v:
2015 IEEE 13th International New Circuits & Systems Conference (NEWCAS); 2015, p1-4, 4p