Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Gai Chenguang"'
Publikováno v:
ECS Transactions. 60:413-424
MHM (Metal Hard Mask) AIO (All-In-One) etch is one of key BEOL (Back-End-Of-Line) processes for 40/45nm technology node and beyond. In this work, we focus on some key issues and solutions that we encountered during 40nm MHM AIO etch process developme
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9cc9a10cd13d6078c6a431def71c7476
https://doi.org/10.1149/06001.0413ecst
https://doi.org/10.1149/06001.0413ecst
Publikováno v:
2015 China Semiconductor Technology International Conference.
Cu process and low-k material are wildly used to reduce Rc delay effect from 45nm technology node and beyond, dry etch to low-k material is one of big challenges in BEOL (Back-End-of-Line) process. For M1 trench etch, the main parameters, such as M1
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::643435f70b71bfb875083934273f93ce
https://doi.org/10.1109/cstic.2015.7153378
https://doi.org/10.1109/cstic.2015.7153378
Autor:
Li Runling, Li Quanbo, Yi Chunyan, Chong Ermin, Huang Jun, Ma Zhibiao, Zhang Yu, Albert Pang, Gai Chenguang
Publikováno v:
2015 China Semiconductor Technology International Conference.
The gate for FinFET structure is graved into a 3D architecture just as a fin fork so that we can control device on/off through the surfaces of its top and two sides. Such design can greatly improve the controllability of circuit and reduce leakage an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aeb72bcc795a8da07552a11d73354606
https://doi.org/10.1109/cstic.2015.7153391
https://doi.org/10.1109/cstic.2015.7153391
Autor:
Li-Yan Zhang, Xu Zhang, Gai Chenguang, Hong-Rui Ren, Jun Huang, Shugen Pen, Yu Zhang, Qiang Ge
Publikováno v:
2015 China Semiconductor Technology International Conference.
Metal Hard Mask (MHM)-All In One (AIO) technology has been widely used in the process flow of copper inter-connect since 28 nm technology node and below. This is because AF immersion exposure technology reaches its limitation for line edge roughness
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b91b6db4e9778610b0db799d679b7c88
https://doi.org/10.1109/cstic.2015.7153376
https://doi.org/10.1109/cstic.2015.7153376
Publikováno v:
2015 China Semiconductor Technology International Conference.
To reduce the RC interconnect delays and cross-talk noise associated with the sub-28 nm advanced CMOS technology nodes, Dual Damascene process combined with Ultra low-k material needs to be introduced into Integrated Circuits manufacturing. With pore
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::61b0da3702ff1247960bcd62da6a1196
https://doi.org/10.1109/cstic.2015.7153375
https://doi.org/10.1109/cstic.2015.7153375
Autor:
Huang Jun, Li Quanbo, Chong Ermin, Yi Chunyan, Li Runling, Gai Chenguang, Ma Zhibiao, Zhang Yu, Albert Pang
Publikováno v:
2015 China Semiconductor Technology International Conference; 2015, p1-4, 4p