Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Gabriele Miorandi"'
Autor:
Steven M. Nowick, Kshitij Bhardwaj, Alberto Ghiribaldi, Davide Bertozzi, Weiwei Jiang, Greg Sadowski, Wayne Burleson, Gabriele Miorandi
Publikováno v:
IEEE Micro. 41:69-81
In this article, a novel interconnect technology is presented for the cost-effective and flexible design of asynchronous networks-on-chip. It delivers asynchrony in heterogeneous system integration while yielding low-energy on-chip data movement. The
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7a86af89d11691b5db464744aa0a2925
https://doi.org/10.1109/mm.2020.3002790
https://doi.org/10.1109/mm.2020.3002790
Publikováno v:
DATE
Smart wireless techniques are at the core of many today's telecommunication and networked embedded systems where performance are enhanced by intertwining radio frequency (RF) and digital aspects. Therefore their design requires to focus on both domai
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::eac589355a591e091eb67cb90a201946
https://doi.org/10.23919/date.2018.8342093
https://doi.org/10.23919/date.2018.8342093
Publikováno v:
NGCAS
Fine-grained power management of largely-integrated manycore systems is becoming mainstream in order to deal with tight power budgets. As a result, some level of asynchrony is becoming inevitable for efficient system-level operation. Asynchronous int
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::397487a9859a11016c6250eb394099f8
https://doi.org/10.1109/ngcas.2017.49
https://doi.org/10.1109/ngcas.2017.49
Autor:
Steven M. Nowick, Davide Bertozzi, Greg Sadowski, Wayne Burleson, Gabriele Miorandi, Weiwei Jiang
Publikováno v:
DATE
An asynchronous high-performance low-power 5-port network-on-chip (NoC) router is introduced. The proposed router integrates low-latency input buffers using a circular FIFO design, and a novel end-to-end credit-based virtual channel (VC) flow control
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d27fbcd6261dbb810d311afcc1c7157b
https://doi.org/10.23919/date.2017.7927084
https://doi.org/10.23919/date.2017.7927084
Publikováno v:
ASYNC
Asynchronous interconnect technology leveraging transition signaling bundled-data is gaining momentum as a promising solution for the chip-level connectivity of GALS (Globally Asynchronous Locally Synchronous) integrated systems. However, the scope o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2ae004205ce3909495f0ed451d7185ea
http://hdl.handle.net/11392/2383349
http://hdl.handle.net/11392/2383349
Publikováno v:
NOCS
Most multi- and many-core integrated systems are currently designed by following a globally asynchronous locally synchronous paradigm. Asynchronous interconnection networks are promising candidates to interconnect IP cores operating at potentially di
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d7faba4d2184c0887a72c85e0aee19f6
https://doi.org/10.1109/nocs.2016.7579332
https://doi.org/10.1109/nocs.2016.7579332
Publikováno v:
AISTECS@HiPEAC
Networks-on-chip (NoCs) are today at the core of multi- and many-core systems, acting as the system-level integration framework. In order to support scaling to future device generations, NoCs will struggle to deliver the required communication perfor
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::68e6568581750700f85a47a945ad86ce
http://hdl.handle.net/11392/2365530
http://hdl.handle.net/11392/2365530
Publikováno v:
ASYNC
Arbiters are the most critical element to manage a shared resource. Many arbiters in the literature are asynchronous, in order to improve concurrency and make the performance independent from the working frequency of the requesting clients. However,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::85aeb937c8cb0e2829a64e4256091306
https://doi.org/10.1109/async.2015.24
https://doi.org/10.1109/async.2015.24
Publikováno v:
LASCAS
NoC-Based Dynamic Reconfigurable Systems (DRSs) implemented over FPGA devices change their configuration at the run time by re-positioning or replacing the existing processing modules into the network. Several Dynamically Reconfigurable NoCs (DRNoCs)
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::dcb7e0ca1b1d8d742f6e80d296349911
http://hdl.handle.net/11392/2365727
http://hdl.handle.net/11392/2365727
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783319162133
ARC
ARC
NoC-Based Dynamic Reconfigurable Systems (DRSs) implemented over FPGA devices change their configuration during operation time by positioning or replacing new processing modules over the network structure, being known as Dynamically Reconfigurable No
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::11679193eb523ea960b9a117dc1f8b27
http://hdl.handle.net/11392/2333969
http://hdl.handle.net/11392/2333969