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Publikováno v:
Proceedings of Digital Processing Applications (TENCON '96).
This paper proposes a scalable memory architecture with systolic dataflow. We divided the entire memory into N/spl times/N sub-memory blocks and placed them onto a scaleable two dimensional array that has communication channels of a partial binary tr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d83e022f7c448de353f8bd3ce8b7c627
https://doi.org/10.1109/tencon.1996.608843
https://doi.org/10.1109/tencon.1996.608843
Publikováno v:
Proceedings of Digital Processing Applications (TENCON '96); 1996, Issue 1, p371-371, 1p