Zobrazeno 1 - 10
of 35
pro vyhledávání: '"G.F. Niu"'
Publikováno v:
Solid-State Electronics. 41:1377-1382
A new definition of L eff which agrees well with electrical measurements using the channel resistance method is proposed, based on numerically simulated surface potential. Using the L eff definition, the physics underlying the fact that L eff can be
Publikováno v:
Solid-State Electronics. 39:69-73
An analytical model of hole confinement gate voltage range is derived for SiGe-channel p-MOSFETs and verified by SEDAN-3 simulation. The hole confinement gate voltage range is shown to be a function of threshold voltage, gate oxide thickness to Si ca
Publikováno v:
IEEE Transactions on Electron Devices. 43:2034-2037
Recent surface potential models for fully depleted short-channel SOI MOSFET's are compared. The parabolic potential approach is clarified to be a special case of the quasi-2-D approach. An extended quasi-2-D model is also derived.
Publikováno v:
Solid-State Electronics. 38:1805-1810
An analytical back gate bias dependent subthreshold swing model of the accumulation-mode p -channel SOI MOSFETs is derived using the exponential dependence of the carrier concentrations on the potential through the silicon film. The subthreshold swin
Publikováno v:
Solid-State Electronics. 38:323-329
A physical model of SiGe PMOS is presented. The condition for proper design ensuring the onset of strong inversion in the SiGe channel is modeled as a function of device structure. The threshold voltages and the inversion charge densities for both ch
Publikováno v:
IEEE Transactions on Electron Devices. 42:2242-2246
Analytical models of threshold voltage and inversion charge for the graded SiGe-channel modulation-doped p-MOSFETs have been derived and verified by SEDAN-3 simulation. The effect of threshold voltage adjustment on hole confinement, and the increase
Publikováno v:
International Electron Devices and Materials Symposium.
The theory of operation for the high effective channel mobility back junction SiGe PMOS is presented. The reduction of the vertical electric field and the improvement in hole confinement are explained physically. An analytical back junction bias depe
Publikováno v:
Solid-State Electronics. 39:305-307
Publikováno v:
Proceedings 1996 IEEE Hong Kong Electron Devices Meeting.
This paper describes user-interface building for device simulation using a heterogeneous computer network. After profiling MINIMOS and analyzing the user demands, we decide to parallize the input parameter sets and then build the Multiple Input-files
Publikováno v:
Proceedings 1996 IEEE Hong Kong Electron Devices Meeting.
Recent surface potential models for fully depleted SOI MOSFETs are compared. The parabolic potential approach is clarified to be a special case of the quasi-2D approach. The earlier quasi-2D model is generalized by relating the front and back surface