Threshold voltage roll-up/roll-off characteristic control in sub-0.2-μm single workfunction gate CMOS for high-performance DRAM applications

Autor: Kazumasa Sunouchi, Rajesh Rengarajan, C. S. Murthy, Paul Ronsheim, R. Katsumata, G.B. Bronner, Hiroyuki Akatsu, Satoshi Inaba

Publikováno v: IEEE Transactions on Electron Devices. 49:308-313

Threshold voltage (V/sub t/) roll-off/roll-up control is a key issue to achieve high-performance sub-0.2-/spl mu/m single workfunction gate CMOS devices for high-speed DRAM applications. It is experimentally confirmed that a combination of well RTA a

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f90035fdc888d9e4903bf7b0817a1cea
https://doi.org/10.1109/16.981222

Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

Autor: G. Burbach, A. Antreasyan, P. Tran, S. Subbanna, Anupama Mallikarjunan, R. Malik, Manfred Horstmann, A. Wei, G.B. Bronner, William F. Clark, S.-P. Sun, C.W. Lai, R. van Bentum, Dureseti Chidambarrao, S. Allen, H.S. Yang, Michael P. Belyansky, J. Buller, H. Kuroda, B. Tessier, Matthias Schaller, E. Ehrichs, J. Sudijono, Anthony I. Chou, Siddarth A. Krishnan, Bernard A. Engel, H.K. Lee, Y. Kohyama, Richard Wise, R. Wong, F.F. Jamin, Michael Raab, C. Wann, X. Chen, P. Huebler, Yujun Li, H.Y. Ng, Victor Chan, J. Klais, K. Bandy, W. Lai, W.-H. Lee, Kartik Subramanian, H. Harifuchi, Siddhartha Panda, L.T. Su, Th. Feudel, Hartmut Ruelke, S.W. Crowder, K. Wieczorek, S.F. Huang, E.H. Lim, G. Grasshoff, Shreesh Narasimha, Jörg Hohage, Markus Lenski, I.Y. Yang, Zhihong Chen, A. McKnight, Rolf Stephan, G. Sudo, Martin Gerhardt, Scott Luning, C. Schwan, S. Goad, K. Matsumoto, J. Nayak, Rajesh Rengarajan, N. Kepler, Kai Frohberg, M. Steigerwalt, Heike Salz, J.C. Arnold, D. Greenlaw, Rama Divakaruni, A. Bonnoit, R. Jagannathan, Paul D. Agnello, Yoshiaki Toyoshima

Publikováno v: IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

For the first time, tensile and compressively stressed nitride contact liners have been simultaneously incorporated into a high performance CMOS flow. This dual stress liner (DSL) approach results in NFET/PFET effective drive current enhancement of 1

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::7b0b34752324983155c85eb5897e2ec0
https://doi.org/10.1109/iedm.2004.1419385

A buried-trench DRAM cell using a self-aligned epitaxy over trench technology

Autor: T.V. Rajeevakumar, B.J. Ginsberg, E.J. Sprogis, B.J. Machesney, Nicky Chau-Chun Lu, G.B. Bronner

Publikováno v: Technical Digest., International Electron Devices Meeting.

A novel three-dimensional buried trench (BT) memory cell, suitable for DRAM (dynamic random access memories) of 64 Mb or beyond, has been demonstrated. It uses a novel self-aligned-epitaxy-over-trench (SEOT) technology which allows the fabrication of

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::e17e1938fa3e9122a55933f2a5a5f5fb
https://doi.org/10.1109/iedm.1988.32883

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