Zobrazeno 1 - 10
of 47
pro vyhledávání: '"G. Grasshoff"'
Akademický článek
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Autor:
I. Aydin, C. Weintraub, J. Schmidt, Elke Erben, Hans-Jürgen Thees, Jamie Schaeffer, J. Kluth, T. Heller, C. Metze, R. Mulfinger, S. Nielsen, Jan Hoentschel, Thomas Feudel, Jürgen Faul, Rick Carter, J. Bernard, Peter Javorka, L. Pirro, David Harame, G. Grasshoff, S. Morvan, B. Rice, Carsten Grass, J-U. Sachse, Elliot John Smith, Mahbub Rashed, C. Bao, R. Nelluri, L. M-Meskamp, J. Mazurier, Yogadissen Andee, Thorsten Kammler, E. Bourjot, A. Preusse, Heimanu Niebojewski, Maud Vinet, P-Y. Chou, Peter Baars, R. Taylor
Publikováno v:
2016 IEEE International Electron Devices Meeting (IEDM)
22FDX™ is the industry's first FDSOI technology architected to meet the requirements of emerging mobile, Internet-of-Things (IoT), and RF applications. This platform achieves the power and performance efficiency of a 16/14nm FinFET technology in a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::694b50f52b286e0ad5957b2cb925a715
https://zenodo.org/record/1272091
https://zenodo.org/record/1272091
Autor:
J. Klais, Hartmut Ruelke, G. Grasshoff, Srikanteswara Dakshina-Murthy, Martin Mazur, Karla Romero, Katja Huy, Marilyn I. Wright, Scott A. Bell, Rolf Stephan, Sarah N. McGowan
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 18:539-545
A novel approach for the patterning and manufacturing of sub-40-nm gate structures is presented. Rather than using resist or an inorganic hardmask as the patterning layer, this gate patterning scheme uses an amorphous carbon (a:C) and cap hardmask to
Autor:
D. Greenlaw, Jon D. Cheek, Manfred Horstmann, Christoph Schwan, Markus Lenski, Peter Huebler, Scott Luning, R. van Bentum, N. Kepler, Matthias Schaller, James F. Buller, Hartmut Ruelke, Kai Frohberg, Gert Burbach, Rolf Stephan, J. Klais, S. Krishnan, Jörg Hohage, Andy Wei, Th. Feudel, Michael Raab, G. Grasshoff, Karsten Wieczorek, Martin Gerhardt
Publikováno v:
Materials Science and Engineering: B. :3-8
Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40 nm gate length (L GATE ) PD SOI t
Publikováno v:
Microelectronic Engineering. 33:249-257
A systematic study of Cu chemical-mechanical polishing (CMP) in terms of process parameters influence, planarization ability of the process and pattern sensitivity of the polish rate was performed. We examined the effects of Cu dishing and SiO 2 thin
Publikováno v:
Surface and Coatings Technology. :539-545
An inductively coupled radio-frequency plasma source was characterized by optical emission spectroscopy, microwave interferometry and electrical measurements. The plasma source works like a transformer. The plasma acts as a single-turn secondary wind
Autor:
G. Burbach, A. Antreasyan, P. Tran, S. Subbanna, Anupama Mallikarjunan, R. Malik, Manfred Horstmann, A. Wei, G.B. Bronner, William F. Clark, S.-P. Sun, C.W. Lai, R. van Bentum, Dureseti Chidambarrao, S. Allen, H.S. Yang, Michael P. Belyansky, J. Buller, H. Kuroda, B. Tessier, Matthias Schaller, E. Ehrichs, J. Sudijono, Anthony I. Chou, Siddarth A. Krishnan, Bernard A. Engel, H.K. Lee, Y. Kohyama, Richard Wise, R. Wong, F.F. Jamin, Michael Raab, C. Wann, X. Chen, P. Huebler, Yujun Li, H.Y. Ng, Victor Chan, J. Klais, K. Bandy, W. Lai, W.-H. Lee, Kartik Subramanian, H. Harifuchi, Siddhartha Panda, L.T. Su, Th. Feudel, Hartmut Ruelke, S.W. Crowder, K. Wieczorek, S.F. Huang, E.H. Lim, G. Grasshoff, Shreesh Narasimha, Jörg Hohage, Markus Lenski, I.Y. Yang, Zhihong Chen, A. McKnight, Rolf Stephan, G. Sudo, Martin Gerhardt, Scott Luning, C. Schwan, S. Goad, K. Matsumoto, J. Nayak, Rajesh Rengarajan, N. Kepler, Kai Frohberg, M. Steigerwalt, Heike Salz, J.C. Arnold, D. Greenlaw, Rama Divakaruni, A. Bonnoit, R. Jagannathan, Paul D. Agnello, Yoshiaki Toyoshima
Publikováno v:
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
For the first time, tensile and compressively stressed nitride contact liners have been simultaneously incorporated into a high performance CMOS flow. This dual stress liner (DSL) approach results in NFET/PFET effective drive current enhancement of 1
Autor:
D. Greenlaw, Rolf Stephan, James F. Buller, Jon D. Cheek, Michael Raab, Christoph Schwan, Markus Lenski, N. Kepler, Karsten Wieczorek, Martin Gerhardt, Gert Burbach, Thomas Feudel, Jörg Hohage, Kai Frohberg, Andy Wei, J. Klais, S. Krishnan, Scott Luning, Peter Huebler, Matthias Schaller, Manfred Horstmann, G. Grasshoff, R. van Bentum, Hartmut Ruelke
Publikováno v:
2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866).
Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40nm gate length (L/sub GATE/) PD SO
Autor:
Manfred Horstmann, David Greenlaw, P. Huebler, R. Stephan, Th. Feudel, A. Wei, K. Frohberg, M. Lenski, K. Wieczorek, G. Burbach, C. Schwan, P. Press, Th. Kammler, H. Bierstedt, R. Otterbach, A. Neu, M. Schaller, H. Salz, J. Hohage, H. Ruelke, J. Klais, G. Grasshoff, E. Ehrichs, S. Goad, M. Raab, N. Kepler
Publikováno v:
ECS Meeting Abstracts. :535-535
not Available.
Autor:
James J. Murphy, H.C. Kennedy, I. Grattan-Guinness, Nicholas Griffin, Rezensiert von G. GRAßHOFF, Bell David
Publikováno v:
History and Philosophy of Logic. 5:131-142