Zobrazeno 1 - 10
of 30
pro vyhledávání: '"G. Dermer"'
Autor:
Jae-Hong Hahn, Siva G. Narendra, Vivek De, B. Bloechel, Tanay Karnik, Donald S. Gardner, Gerhard Schrom, P. Hack, S. Borkar, G. Dermer, Peter Hazucha
Publikováno v:
IEEE Journal of Solid-State Circuits. 40:838-845
We demonstrate an integrated buck dc-dc converter for multi-V/sub CC/ microprocessors. At nominal conditions, the converter produces a 0.9-V output from a 1.2-V input. The circuit was implemented in a 90-nm CMOS technology. By operating at high switc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cddff1924cf393ddd60653f7d00bb06b
https://doi.org/10.1109/jssc.2004.842837
https://doi.org/10.1109/jssc.2004.842837
Autor:
Krishnamurthy Soumyanath, Siva G. Narendra, S. Walstra, S. Borkar, J. Maiz, James W. Tschanz, B. Bloechel, Vivek De, Tanay Karnik, Peter Hazucha, G. Dermer
Publikováno v:
IEEE Journal of Solid-State Circuits. 39:1536-1543
We designed a soft error rate (SER) tolerant latch utilizing local redundancy. We implemented a test chip containing both the standard and SER-tolerant latches in a 90-nm dual-V/sub T/ CMOS process. Accelerated measurements with a neutron beam at Los
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cdc0262a6b5597c3333471b70147cbd5
https://doi.org/10.1109/jssc.2004.831449
https://doi.org/10.1109/jssc.2004.831449
Autor:
Y. Ye, Mark A. Anders, Sanu Mathew, Krishnamurthy Soumyanath, G. Dermer, Vivek De, Siva G. Narendra, S. Borkar, Dinesh Somasekhar, S. Thompson, V. Veeramachaneni, E. Seligman, James W. Tschanz, Ram Krishnamurthy, Vasantha Erraguntla, Nitin Borkar, M.R. Stan, V. Govindarajulu, Amaresh Pangal, B.A. Bloechel, Sriram R. Vangal, H. Wilson
Publikováno v:
IEEE Journal of Solid-State Circuits. 37:1421-1432
A 32-bit integer execution core containing a Han-Carlson arithmetic-logic unit (ALU), an 8-entry /spl times/ 2 ALU instruction scheduler loop and a 32-entry /spl times/ 32-bit register file is described. In a 130 nm six-metal, dual-V/sub T/ CMOS tech
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::736d5cc82f3302f183f8978b5e8bce24
https://doi.org/10.1109/jssc.2002.803944
https://doi.org/10.1109/jssc.2002.803944
Publikováno v:
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005..
A 10Mb planar 1T-IC DRAM chip is implemented in an unmodified 150nm micro-processor logic process. It achieves 15GBytes/sec bandwidth, 9.5nsec read access time with 197mW power at 1.5V, 110/spl deg/C. Worst-case refresh period is 100/spl mu/S at 110/
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d39c8edd8f6b97a90f9adb738dcfd5ac
https://doi.org/10.1109/esscir.2005.1541633
https://doi.org/10.1109/esscir.2005.1541633
Autor:
S. Narendra, M. Haycock, V. Govindarajulu, V. Erraguntla, H. Wilson, S. Vangal, A. Pangal, E. Seligman, R. Nair, A. Keshavarzi, B. Bloechel, G. Dermer, R. Mooney, N. Borkar, S. Borkar, null Vivek De
Publikováno v:
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5eaa85876c204a737caebd3dae790623
https://doi.org/10.1109/isscc.2002.992222
https://doi.org/10.1109/isscc.2002.992222
Autor:
S. Vangal, N. Borkar, E. Seligman, V. Govindarajulu, V. Erraguntla, H. Wilson, A. Pangal, V. Veeramachaneni, M. Anders, J. Tschanz, Y. Ye, D. Somasekhar, B. Bloechel, G. Dermer, R. Krishnamurthy, S. Narendra, M. Stan, S. Thompson, V. De, S. Borkar
Publikováno v:
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a12d29965ce973cd2317d3fe166f3a0e
https://doi.org/10.1109/isscc.2002.992282
https://doi.org/10.1109/isscc.2002.992282
Autor:
Trang Nguyen, Y. Ye, Dinesh Somasekhar, Muhammad M. Khellah, G. Dermer, Vivek De, B. Bloechel, A. Farhang, D. Casper, Kevin Zhang, Gunjan H. Pandya
Publikováno v:
Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..
Bitline leakage compensation (BLC) and leakage reduction (BLR) techniques, implemented for cache arrays on a testchip in a 90nm logic technology, demonstrate improvement in operational frequency from 1.2GHz to 2GHz for BLC, and to 3GHz for BLR, with
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f63197f3294efe15b364bf720ecb2f67
https://doi.org/10.1109/vlsic.2005.1469381
https://doi.org/10.1109/vlsic.2005.1469381
Autor:
G. Dermer, Jaehong Hahn, Donald S. Gardner, Tanay Karnik, Gerhard Schrom, Vivek De, Peter Hazucha, Siva G. Narendra, B. Bloechel
Publikováno v:
2004 IEEE 35th Annual Power Electronics Specialists Conference (IEEE Cat. No.04CH37551).
We propose an on-chip 1.8 V-to-0.9 V DC-DC converter aimed to reduce the input current and decoupling requirements of future microprocessors. By utilizing a 90-nm CMOS process, employing a four-phase hysteretic control, and operating at ultra-high fr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3f97a7f5560df2b18ffb77b5281c59f4
https://doi.org/10.1109/pesc.2004.1354830
https://doi.org/10.1109/pesc.2004.1354830
Autor:
Donald S. Gardner, Vivek De, P. Hack, G. Dermer, Tanay Karnik, Peter Hazucha, Jae-Hong Hahn, S. Borkar, B. Bloechel, Gerhard Schrom, Siva G. Narendra
Publikováno v:
Scopus-Elsevier
We demonstrate an integrated buck DC-DC converter implemented in a 90nm CMOS technology for multi-Vcc microprocessors. High switching frequency (100-317MHz), 4-phase topology, and fast hysteretic control reduce inductor and capacitor sizes by 1000x,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::039bab116eb98b161cee2eeee5daf3e8
https://doi.org/10.1109/vlsic.2004.1346578
https://doi.org/10.1109/vlsic.2004.1346578
Autor:
Krishnamurthy Soumyanath, Vivek De, Siva G. Narendra, J. Maiz, S. Borkar, Peter Hazucha, J. Tschanz, P. Armstrong, Tanay Karnik, B. Bloechel, Ali Keshavarzi, G. Dermer
Publikováno v:
2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).
Soft error rate measurements for flip-flops on two testchips in 180nm and 130nm logic technologies show that using forward body bias improves alpha SER by 35% and neutron SER by 23%, while applying reverse body bias degrades SER by 9% to 36%. Body bi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8609d9d4dbd22e837d6aa4f26e48388f
https://doi.org/10.1109/vlsic.2004.1346603
https://doi.org/10.1109/vlsic.2004.1346603