Zobrazeno 1 - 10
of 62
pro vyhledávání: '"G. Cibrario"'
Publikováno v:
MWSCAS
This paper discusses the mixed-signal circuit design in a novel monolithic (sequential) 3D process. The goal of this work is to explore a novel multi-process sequential 3D technology with the state-of-art 3D interconnections density of 2 × 107 via/m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bca01230232afd7fcc71fe958e0e29b5
https://doi.org/10.1109/mwscas47672.2021.9531677
https://doi.org/10.1109/mwscas47672.2021.9531677
Autor:
Benoit Sklenard, Bastien Giraud, Sebastien Thuries, Mikael Casse, Joris Lacord, Cm. Ribotta, V. Lapras, P. Acosta-Alba, O. Billoint, M. Mouhdach, N. Rambal, Pascal Besson, Francois Andrieu, Perrine Batude, Didier Lattard, Laurent Brunet, Gilles Sicard, Xavier Garros, Christoforos G. Theodorou, L. Brevard, Maud Vinet, V. Mazzocchi, P. Sideris, M. Ribotta, Claire Fenouillet-Beranger, F. Ponthenier, Pascal Vivet, Sebastien Kerdiles, G. Cibrario, J.M. Hartmann, Frank Fournel, Bernard Previtali, Frédéric Mazen, Claude Tabone
Publikováno v:
2021 IEEE International Interconnect Technology Conference (IITC)
2021 IEEE International Interconnect Technology Conference (IITC), Jul 2021, Kyoto, France. pp.1-1, ⟨10.1109/IITC51362.2021.9537356⟩
2021 IEEE International Interconnect Technology Conference (IITC), Jul 2021, Kyoto, France. pp.1-1, ⟨10.1109/IITC51362.2021.9537356⟩
The aim of this paper is to present the 3D-sequential integration and its main prospective application sectors. The presentation will also give a synoptic view of all the key enabling process steps required to build high performance Si CMOS integrate
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5a896dcadaa6b8a425398da1a162204f
https://hal.archives-ouvertes.fr/hal-03434018
https://hal.archives-ouvertes.fr/hal-03434018
Autor:
Francois Andrieu, L. Ciampolini, G. Cibrario, F. Balestra, Joris Lacord, Xavier Garros, Perrine Batude, Laurent Brunet, A. Makosiej, D. Lattard, Bastien Giraud, Maud Vinet, Claire Fenouillet-Beranger, J.-P. Colinge, Olivier Weber, J. Cluzel, D. Bosch
Publikováno v:
2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Apr 2019, Grenoble, France. pp.1-4, ⟨10.1109/EUROSOI-ULIS45800.2019.9041890⟩
2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Apr 2019, Grenoble, France. pp.1-4, ⟨10.1109/EUROSOI-ULIS45800.2019.9041890⟩
International audience; We fabricated and characterized 14nm planar Fully-Depleted-Silicon-On-Insulator (FDSOI) 0.078µm² Static Random Access Memory (SRAM) cells. Temporal and spatial variability as well as sensibility to temperature, supply voltag
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5a29cff3968e6920ebe18ab7cb26addf
https://hal.archives-ouvertes.fr/hal-02998370
https://hal.archives-ouvertes.fr/hal-02998370
Autor:
F. Balestra, A. Makosiej, Joris Lacord, Maud Vinet, Laurent Brunet, E. Esmanhotto, Francois Andrieu, Marco Rios, J. Cluzel, G. Cibrario, Perrine Batude, Olivier Weber, R. Berthelon, D. Lattard, D. Bosch, L. Ciampolini, Claire Fenouillet-Beranger, J.-P. Colinge, Bastien Giraud, S. Lang, Xavier Garros
Publikováno v:
2019 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).
For the first time, we propose a 3D-monolithic SRAM architecture with a local back-plane for top-tier transistors enabling local back-bias assist techniques without area penalty as well as the capability to route two additional row-wise signals on in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6339fddbd9f229a6f65ff13fd410189d
https://doi.org/10.1109/vlsi-tsa.2019.8804649
https://doi.org/10.1109/vlsi-tsa.2019.8804649
Autor:
M. Mouhdach, Sebastien Thuries, Didier Lattard, G. Cibrario, O. Billoint, K. Azizi-Mourier, Pascal Vivet
Publikováno v:
2019 International 3D Systems Integration Conference (3DIC)
3DIC
3DIC
Design of 3D ICs is mainly done in separated design environments for each tier, assuming that communication channels between tiers are user-defined and fixed at the beginning of the design process. Suitable for 3D stacking based on TSV or Hybrid Bond
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::54d0aecdf0685cada95078adf7e7c291
Autor:
Francois Andrieu, Joris Lacord, R. Berthelon, Laurent Brunet, A. Makosiej, Olivier Weber, C. Fenouillet-Beranger, X. Garros, G. Cibrario, D. Lattard, J.-P. Colinge, J. Cluzel, Lorenzo Ciampolini, D. Bosch, Perrine Batude, F. Balestra, Bastien Giraud
Publikováno v:
Solid-State Electronics. 168:107720
For the first time, we propose a 3D-monolithic SRAM architecture with a local back-plane for top-tier transistors enabling local back-bias assist techniques without area penalty, as well as the capability to route two additional row-wise signals on i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::693fb96b0d9182cfb46ea634695f9b9a
https://doi.org/10.1016/j.sse.2019.107720
https://doi.org/10.1016/j.sse.2019.107720
Autor:
John Morgan, Remy Berthelon, Jan Hoentschel, L. Pirro, G. Cibrario, Francois Andrieu, M. Wiatr, M. Vinet
Publikováno v:
2018 IEEE Symposium on VLSI Technology.
We propose an original Technology/Design Co-optimization of standard cells mixing devices of different threshold voltages (V T -flavors) within a cell. It is successfully applied with nMOS Low-V T (LVT) and pMOS Super-Low-V T (SLVT) in Ultra-Low-Volt
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2800450d12f1f2a6c0b7ec53aae97eb0
https://doi.org/10.1109/vlsit.2018.8510636
https://doi.org/10.1109/vlsit.2018.8510636
Autor:
C. Fenouillet-Beranger, Perrine Batude, G. Cibrario, G. Tricaud, R. Boumchedda, Pierre Morin, Franck Arnaud, Laurent Brunet, O. Rozeau, Bastien Giraud, Sebastien Thuries, M. Vinet, Joris Lacord, R. Berthelon, S. Guissi, D. Fried, B. Mathieu, O. Billoint, Francois Andrieu, J.-P. Noel, A. Ayres de Sousa, E. Avelar
Publikováno v:
2017 IEEE International Electron Devices Meeting (IEDM).
We have fabricated 3D-monolithic transistors on two tiers. We experimentally evidence the asymmetric double-gate (DG) behavior of a top-tier transistor, resulting in a better ON-state current (Ion) / OFF-state current (I off ) tradeoff than in single
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0dc4ba1dc97a9317eb210e8ddb6f1d5d
https://doi.org/10.1109/iedm.2017.8268428
https://doi.org/10.1109/iedm.2017.8268428
Autor:
Perrine Batude, Vincent Lu Cao-Minh, Claire Fenouillet-Beranger, Sebastien Thuries, Laurent Brunet, O. Billoint, Cristiano Santos, B. Mathieu, G. Cibrario, Francois Andrieu, M. Brocard, Jean-Philippe Colonna
Publikováno v:
ISVLSI
This study focuses on temperature deviation during operation of transistors inside a monolithic 3D standard cell built on two tiers. Early assessment of this topic is crucial to manage circuit design and requires both steady-state and transient therm
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b21477c0d4d7f84cc29e8d94460e90b3
https://doi.org/10.1109/isvlsi.2017.100
https://doi.org/10.1109/isvlsi.2017.100
Autor:
X. Garros, N. Rambal, C. Fenouillet-Beranger, M. Brocard, L. Pasini, G. Cibrario, Thomas Skotnicki, M.-P. Samson, A. Ayres, Laurent Brunet, M. Vinet, C. Tallaron, C-M. V., O. Billoint, R. Gassilloud, Francois Andrieu, R. Kies, G. Romano, Perrine Batude, Bernard Previtali, A. Toffoli, M. Casse, P. Besombes, C. Leroux, Claude Tabone, V. Lapras, A. Laurent, D. Barge
Publikováno v:
2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).
Stacking N over CMOS devices using 3D Sequential CoolCube™ Integration has been shown promising for the scaling of 6T SRAMs. By transposing one pass-gate and one pull-down NMOS to the top layer, a cell footprint reduction of 27% could be obtained,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8f5a2b330e51e3a5752e754ac6b9e197
https://doi.org/10.1109/vlsi-tsa.2017.7942495
https://doi.org/10.1109/vlsi-tsa.2017.7942495