Zobrazeno 1 - 10
of 30
pro vyhledávání: '"G. Chabanne"'
Autor:
W. Schwarzenbach, B.-Y. Nguyen, L. Ecarnot, S. Loubriat, M. Detard, E. Cela, C. Bertrand-Giuliani, G. Chabanne, C. Maddalon, N. Daval, C. Maleville
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 7, Pp 863-868 (2019)
Beyond 65FD-SOI, 28FD-SOI, and 22FD-SOI production granted technologies, SmartCut™ development supports both advanced FD-SOI and low temperature SOI roadmaps. Ultrathin SOI and BOX materials developments are reported, including 4-nm SOI and 15-nm B
Externí odkaz:
https://doaj.org/article/edbba5752ee645b7974f97152c8b83f8
Publikováno v:
2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).
Beyond conventional FinFet & FD-SOI device architectures, Complementary FET (CFET) is considered. To support this 3D approach, improving integration, manufacturing and paving the way to performance booster introduction, engineered substrates are prop
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3aef1319d96f02c10eee10faf81c09c8
https://doi.org/10.1109/s3s46989.2019.9320657
https://doi.org/10.1109/s3s46989.2019.9320657
Autor:
E. Cela, Christophe Maleville, Ludovic Ecarnot, C. Maddalon, Nicolas Daval, S. Loubriat, C. Bertrand-Giuliani, Walter Schwarzenbach, Bich-Yen Nguyen, G. Chabanne, M. Detard
Publikováno v:
IEEE Journal of the Electron Devices Society
Beyond 65FD-SOI, 28FD-SOI, and 22FD-SOI production granted technologies, SmartCut™ development supports both advanced FD-SOI and low temperature SOI roadmaps. Ultrathin SOI and BOX materials developments are reported, including 4-nm SOI and 15-nm B
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::968d4c7f89ab9005168a0207eba62996
Autor:
Amy Child, Walter Schwarzenbach, Rick Carter, Robert Mulfinger, Bich-Yen Nguyen, Nicolas Daval, J. Kluth, Jamie Schaeffer, Manish Hemkar, S. Moffatt, G. Chabanne, Schubert S. Chu, Sherry Straub, Paul A. Clifton, Andreas Goebel, Ryan Sporer
We report for the first time the implementation of SiGe buried stressors in the context of research and development of an advanced foundry FDSOI process and the observation of improved transconductance and current drive performance of n-channel FDSOI
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::52dbc92e222e6301545d2962f2b3794b
Autor:
Christophe Figuet, S. Guerroudj, Sebastien Kerdiles, O. Bonnin, Walter Schwarzenbach, X. Cauchy, Nicolas Daval, Christophe Maleville, G. Chabanne, Bich-Yen Nguyen
Publikováno v:
ICICDT
Smart Cut™ technology is used to manufacture Strained-SOI (sSOI) substrates. These substrates are proposed to boost performance for both planar and FinFET Fully Depleted SOI devices. To comply with tight transistor variability requirements, strong
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d1be123b2c96479baba654bdaa996295
https://doi.org/10.1109/icicdt.2012.6232869
https://doi.org/10.1109/icicdt.2012.6232869
Autor:
C. Fenouillet-Beranger, J. Todeschini, J.C. Le-Denmat, N. Loubet, C. Gallon, P. Perreau, S. Manakli, B. Minghetti, L. Pain, V. Arnal, A. Vandooren, S. Denorme, D. Aime, L. Tosti, C. Savardi, M. Broekaart, P. Gouraud, F. Leverd, V. Dejonghe, P. Brun, M. Guillermet, M. Aminpur, B. Icard, S. Barnola, F. Rouppert, F. Martin, T. Salvetat, S. Lhostis, C. Laviron, N. Auriac, T. Kormann, G. Chabanne, S. Gaillard, F. Boeuf, O. Belmont, E. Laffosse, D. Barge, A. Zauner, A. Tarnowka, K. Romanjec, H. Brut, A. Lagha, S. Bonnetier, F. Joly, J. Coignus, N. Mayet, A. Cathignol, D. Galpin, D. Pop, R. Delsol, R. Pantel, F. Pionnier, G. Thomas, D. Bensahel, S. Deleonibus, O. Faynot, T. Skotnicki, H. Mingam, L. Brevard, C. Buj, C. Soonekindt
Publikováno v:
2007 IEEE International Electron Devices Meeting.
In this paper, we report on FD-SOI with high-k and single metal gate as a possible candidate for the 32 nm LOP and LSTP nodes. Good Ion/Ioff performance for nMOS and pMOS transistors in the ultra-low-leakage regime (Ioff=6.6 pA/μm) are presented. In
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9b01d356319804f33639c8bbcd010bbb
https://doi.org/10.1109/iedm.2007.4418919
https://doi.org/10.1109/iedm.2007.4418919
Autor:
D. Bensahel, D. Aime, Romain Gwoziecki, T. Salvetat, Simon Deleonibus, Francois Leverd, M. Aminpur, Claire Fenouillet-Beranger, A. Zauner, Antoine Cros, Vincent Cosnier, R. Gassilloud, L. Brevard, Marius K. Orlowski, A. Wild, J. Coignus, H. Mingam, Frederic Boeuf, C. Hobbs, Thomas Skotnicki, A. Vandooren, S. Minoref, P. Perreau, Sébastien Barnola, M. Muller, François Martin, Stephane Denorme, G. Chabanne, O. Faynot, D. Fleury
Publikováno v:
ESSDERC 2007 - 37th European Solid State Device Research Conference.
This paper describes the fabrication and electrical behavior of a fully-depleted SOI technology using a direct metal gate and high-k dielectric integrated on 300 mm SOI wafers for low power applications. We report ultra-thin FDSOI MOS transistors wit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::60a2442250b9fc29632d8532e0ef3916
https://doi.org/10.1109/essderc.2007.4430926
https://doi.org/10.1109/essderc.2007.4430926
Autor:
A. Tarnowka, C. Laviron, Thomas Skotnicki, Stephane Denorme, M. Muller, S. Bonnetier, Simone Pokrant, G. Ribes, A. Cathignol, Pascal Gouraud, C. Blanc, D. Aime, T. Kormann, G. Bidal, D. Barge, Mustapha Rafik, Frederic Boeuf, Gerard Ghibaudo, G. Chabanne
Publikováno v:
Extended Abstracts of the 2007 International Conference on Solid State Devices and Materials.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6db2c92bca05362059a5e914245c7884
https://doi.org/10.7567/ssdm.2007.a-9-5
https://doi.org/10.7567/ssdm.2007.a-9-5
Autor:
M. Broekaart, Stephane Denorme, T. Skotnicki, Y. Le Tiec, Pierre Perreau, A. Vandooren, L. Gabette, G. Chabanne, M. Aminpur, O. Faynot, S. Barnola, C. Hobbs, Claire Fenouillet-Beranger, Alexander Wild, D. Dutartre, I. Pouilloux, C. Laviron, C. Gallon, Nicolas Loubet, S. Smith, M. Bidaud, T. Korman, Daniel Bensahel, G. lmbert, François Martin, H. Mingam, C. Morin, A. Zauner, N. Gierczynski, H. Bernard, Philippe Garnier
Publikováno v:
2005 IEEE International SOI Conference Proceedings.
A low power 45nm fully-depleted SOI technology is demonstrated for the first time on 300mm SOI wafers, using direct metal gate on high k dielectric and selective silicon epitaxy. Short p-channel devices exhibit very good performance. SRAM bit cells a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::78a9a7d36d308661e75d9ac41ee0677f
https://doi.org/10.1109/soi.2005.1563595
https://doi.org/10.1109/soi.2005.1563595