Zobrazeno 1 - 10
of 74
pro vyhledávání: '"Fumiyoshi Matsuoka"'
Autor:
Soo Man Seo, Hisanori Aikawa, Soo Gil Kim, Toshihiko Nagase, Yuich Ito, Tae Jung Ha, Kenichi Yoshino, Bo Kyung Jung, Tadaaki Oikawa, Ku Youl Jung, Hyun In Moon, Bum Su Kim, Fumiyoshi Matsuoka, Kosuke Hatsuda, Katsuhiko Hoya, Seiyon Kim, Sung-Hoon Lee, Myung-Hee Na, Seon Yong Cha
Publikováno v:
2022 International Electron Devices Meeting (IEDM).
Publikováno v:
IEEE Journal of Solid-State Circuits. 46:2148-2157
Methods to generate an accurate reference current by averaging multi-pair dummy cells' currents for distinguishing the data in sense amplifiers (S/As) of a large scale memory with resistance change cell is presented and analyzed. The predicted charac
Autor:
Daisuke Hashimoto, Akihiro Nitayama, Daisaburo Takashima, Takeshi Hioka, Yoshiro Shimojo, Hidehiro Shiga, Yuki Yamada, Koji Yamakawa, Katsuhiko Hoya, Toyoki Taguchi, Shoichi Shimizu, Ryu Ogiwara, Hisaaki Nishimura, Tohru Ozaki, Yohji Watanabe, Shinichiro Shiratake, Sumiko Doumae, Iwao Kunishima, Tohru Furuyama, Tadashi Miyakawa, Hiroyuki Kanaya, Souichi Yamazaki, Shuso Fujii, Fumiyoshi Matsuoka, Yasushi Nagadomi, Ryo Fukuda, Ryosuke Takizawa, Yoshinori Kumura, Mitsumo Kawano, Susumu Shuto, Takeshi Hamamoto, Yoshihiro Minami, Kosuke Hatsuda
Publikováno v:
ISSCC
An 87.7 mm2 1.6 GB/s 128 Mb chain FeRAM with 130 nm 4-metal CMOS process is demonstrated. In addition to small bitline capacitance inherent to chain FeRAM architecture, three new FeRAM scaling techniques - octal bitline architecture, small parasitic
Autor:
H. Furuhashi, Yohji Watanabe, Tohru Furuyama, Takeshi Hamamoto, Hiroomi Nakajima, Akihiro Nitayama, Tomoaki Shino, Fumiyoshi Matsuoka, Yoshihiro Minami, Ryo Fukuda, Tomoki Higashi, Takashi Ohsawa, Katsuyuki Fujita
Publikováno v:
IEEE Transactions on Electron Devices. 56:2302-2311
Physics of autonomous refresh is presented, which explains the mechanism of a spontaneous recovery of degraded binary states of the floating-body cell (FBC). Input current to the floating body and output current from the body balance to generate an u
Autor:
A. Sakata, M. Ohta, Hisao Yoshimura, Fumiyoshi Matsuoka, Eiji Morifuji, Hisanori Aikawa, M. Iwai
Publikováno v:
IEEE Transactions on Electron Devices. 56:1991-1998
Layout dependences for stress-enhanced MOSFETs including contact positioning, the second neighboring poly effect, and bent diffusion are modeled in 45-nm CMOS logic technology. It is found that the sensitivity of contact position in the channel direc
Publikováno v:
IEEE Transactions on Electron Devices. 53:1427-1432
The authors show new guidelines for V/sub dd/ and threshold voltage (V/sub th/) scaling for both the logic blocks and the high-density SRAM cells from low power-dissipation viewpoint. For the logic operation, they have estimated the power and the spe
Publikováno v:
IEEE Transactions on Electron Devices. 52:1194-1199
This paper describes the device design guidelines for floating channel type surrounding gate transistor (FC-SGT) DRAM cells with high soft-error immunity. One FC-SGT DRAM cell consists of an FC-SGT and a three-dimensional storage capacitor. The cell
Autor:
Hisao Yoshimura, Atsushi Murakoshi, Yoshiaki Toyoshima, M. Tanaka, Fumiyoshi Matsuoka, Satoshi Inaba
Publikováno v:
IEEE Transactions on Electron Devices. 46:1218-1224
Anomalously high parasitic resistance is observed when SiN gate sidewall spacer is incorporated into sub-0.25-/spl mu/m pMOSFET's. The parasitic resistance in p/sup +/ S/D extension region increases remarkably by decreasing BF/sub 2/ ion implantation
Autor:
K. Muraoka, Hidetoshi Koike, E. Fukuda, S. Hohkibara, Nobuo Hayasaka, Hideshi Miyajima, K. Tomioka, M. Kimura, Fumiyoshi Matsuoka
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 11:54-62
We describe equipment and facility operational methods in a production fab which are designed to achieve quick-turnaround-time (QTAT) manufacturing and ease product transfer from development to mass production. An advanced CIM system with precise lot
Publikováno v:
IEEE Transactions on Electron Devices. 44:1460-1466
Process techniques for dual-polycide gate CMOS have been developed. The origin of lateral dopant diffusion is analyzed, and an enlarged-grain dual-polycide gate technology using regrowth amorphous-Si (a-Si) is proposed. Reduction of the dopant absorp