Zobrazeno 1 - 10
of 29
pro vyhledávání: '"Fumio Yuki"'
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 67:3433-3443
A 103.13-Gbps 4-lane transceiver for copper cable applications was fabricated in 28-nm CMOS technology. The transceiver can transmit 103.13-Gbps data through 4-lane 47-dB-loss channels. To achieve this result, ISI should be suppressed; equalization a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b5364f110fe41d251a27274c771fb662
https://doi.org/10.1109/tcsi.2020.2993569
https://doi.org/10.1109/tcsi.2020.2993569
Autor:
Norio Chujo, Hiroki Yamashita, Shinji Tsuji, Fumio Yuki, Takashi Takemoto, Noboru Masuda, Shinji Nishimura, Yong Lee, Hidehiro Toyoda
Publikováno v:
IEEE Journal of Solid-State Circuits. 49:471-485
A one-chip optical transceiver for board-to-board transmission was developed by integrating an analog frontend (FE) with a data-format-conversion (DFC) block in 65-nm CMOS process technology. It was experimentally demonstrated that this transceiver c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5333b2f3ae7a0bba1d1db87920d28e89
https://doi.org/10.1109/jssc.2013.2291099
https://doi.org/10.1109/jssc.2013.2291099
Autor:
Keiichi Higeta, Yuichi Ito, Norio Nakajima, Takashi Kawamoto, Masatoshi Hasegawa, Tomofumi Hokari, Seiichi Umai, Masatoshi Tsuge, Kenji Kogo, Junya Nasu, Tatsunori Usugi, Tsuneo Kawamata, Fumio Yuki, Takayasu Norimatsu, Takemasa Komori, Takashi Muto, Hideki Koba, Takeo Yamashita, Naohiro Kohmu
Publikováno v:
ISSCC
The amount of data traffic is increasing year by year as the number of data-rich services like cloud services and streaming services are increasing. The number of switch modules between servers should decrease to lower latency, and several servers in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8d266996e7b790c78220f8c7f65a9933
https://doi.org/10.1109/isscc.2016.7417906
https://doi.org/10.1109/isscc.2016.7417906
Autor:
Shinji Nishimura, Ryo Nemoto, Noboru Masuda, Takashi Muto, Goichi Ono, Tatsuya Saito, Seiichi Umai, Fumio Yuki, Masashi Kono, Hiroki Yamashita, Masayoshi Yagyu, Takashi Takemoto, Koji Fukuda, Akihiro Kambe, Hidehiro Toyoda, K. Watanabe, Eiichi Suzuki
Publikováno v:
ISSCC
The 100-gigabit Ethernet (100GbE) was standardized as IEEE 802.3ba in 2010 [1]. The optics module must be equipped with a “gearbox” LSI-which switches between 10×10Gb/s data signals on the physical-coding-sublayer side and 4×25Gb/s data signals
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7441a6b03c839cd1f3e0cfdae5e3cefe
https://doi.org/10.1109/jssc.2011.2168869
https://doi.org/10.1109/jssc.2011.2168869
Autor:
Kazunori Shinoda, Hidehiro Toyoda, N. Ikeda, Shinji Nishimura, Fumio Yuki, Takashi Takemoto, M Yamada, Yong Lee, Goichi Ono, Koji Fukuda, Shinji Tsuji
Publikováno v:
IEEE Journal of Selected Topics in Quantum Electronics. 17:347-356
Photonic technology is an important solution to achieve power-saving routers/switches for green networks. As networking is a worldwide matter, and as the power consumed by routers and switches is rapidly increasing, power-efficient green networks hav
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::317bd278f3970bb7857d0b9a41380dd0
https://doi.org/10.1109/jstqe.2010.2066261
https://doi.org/10.1109/jstqe.2010.2066261
Autor:
Hiroki Yamashita, Tatsuya Saito, Ryo Nemoto, Goichi Ono, Takashi Takemoto, Eiichi Suzuki, Noboru Masuda, Fumio Yuki, Koji Fukuda
Publikováno v:
IEEE Journal of Solid-State Circuits. 45:2838-2849
A 12.3-mW 12.5-Gb/s complete transceiver based on the 65-nm standard digital CMOS process was developed. The chip includes a clock-and-data-recovery (CDR) device, a multiplexer/demultiplexer (MUX/DEMUX), and a global clock-distribution network. To re
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::532bfc6fb05920e1c400ddcdd8bedaf5
https://doi.org/10.1109/jssc.2010.2075410
https://doi.org/10.1109/jssc.2010.2075410
Autor:
Eiichi Suzuki, Hiroki Yamashita, Tatsuya Saito, Masashi Kono, Koji Fukuda, Fumio Yuki, Ryo Nemoto, Takashi Takemoto, Goichi Ono
Publikováno v:
IEEE Journal of Solid-State Circuits. 44:3539-3546
A 10 Gb/s receiver with a digital CDR uses a track-and-hold-type linear phase detector (LPD) and charge-redistribution first-order ΔΣ modulator. It has low quantization error and high loop bandwidth due to the use of the LPD and maintains the advan
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5d8009aad5afab441d7f8e4f9e0d5237
https://doi.org/10.1109/jssc.2009.2031016
https://doi.org/10.1109/jssc.2009.2031016
Autor:
Kenji Kogo, Naohiro Kohmu, Norio Nakajima, Fumio Yuki, Takayasu Norimatsu, Takashi Muto, Takashi Kawamoto
Publikováno v:
2015 IEEE CPMT Symposium Japan (ICSJ).
A 25-Gbps/lane 40-dB compensation signal conditioner was developed. The target architecture was a long channel backplane with two connectors that have large reflections due to impedance discontinuities. Jitters originating from the power integrity (P
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d7d29ddfb10a4b7b080ecf0b034478fa
https://doi.org/10.1109/icsj.2015.7357400
https://doi.org/10.1109/icsj.2015.7357400
Autor:
Keiichi Higeta, Fumio Yuki, Yuichi Ito, Takashi Kawamoto, Takayasu Norimatsu, Kenji Kogo, Tsuneo Kawamata, Tatsunori Usugi, Tomofumi Hokari, Takemasa Komori, Junya Nasu, Jun Kumazawa, Takashi Muto, Hiroaki Kurahashi, Takeo Yamashita, Hideki Koba, Norio Nakajima, Seiichi Umai, Masatoshi Hasegawa, Masatoshi Tsuge
Publikováno v:
ISSCC
As processing and network speeds are accelerated to support data-rich services, the bandwidth of backplane interconnects needs to be increased while maintaining the channel length and multi-rate links. However, channel losses and impedance discontinu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::af8f5c009e73cb9d0142d71f444d3b5f
https://doi.org/10.1109/isscc.2015.7062922
https://doi.org/10.1109/isscc.2015.7062922
Publikováno v:
IEEE Journal of Solid-State Circuits. 39:613-621
This paper describes a 2.5-Gb/s/ch digital data recovery (DR) circuit for the SFI-5 interface. Although minimizing the circuit area has become critical in multibit interfaces such as the SFI-5, few studies have proposed a practical method of reducing
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6bfcc5c15239684214c973d1c3d129f8
https://doi.org/10.1109/jssc.2004.824704
https://doi.org/10.1109/jssc.2004.824704