Výsledky vyhledávání - "Fumihiko Tachibana"

Quantization Strategy for Pareto-optimally Low-cost and Accurate CNN

Autor: Asuka Maki, Daisuke Miyashita, Ryuichi Fujimoto, Fumihiko Tachibana, Kengo Nakata, Jun Deguchi, Shinichi Sasaki

Publikováno v: AICAS

Quantization is an effective technique to reduce memory and computational costs for inference of convolutional neural networks (CNNs). However, it has not been clarified which model can achieve higher recognition accuracy with lower memory and comput

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::4a213f5dd5eb46e398a697005f2c3610
https://doi.org/10.1109/aicas51828.2021.9458452

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A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems

Autor: Daisuke Miyashita, Yuji Satoh, Takashi Toi, Junji Wadatsumi, Makoto Morimoto, Jun Deguchi, Ryuichi Fujimoto, Yuta Tsubouchi, Fumihiko Tachibana

Publikováno v: IEEE Journal of Solid-State Circuits. 54:1086-1095

Toward the aim of realizing high-bandwidth, large-capacity nand flash memory-based storage systems, this paper presents a novel daisy-chain downlink interface (I/F) between a controller and a large number of nand packages. The daisy-chain I/F employs

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::47d6690b1626e08e5749bd868a84c086
https://doi.org/10.1109/jssc.2018.2889704

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Can in-memory/analog accelerators be a silver bullet for energy-efficient inference?

Autor: Asuka Maki, Daisuke Miyashita, S. Sasaki, Jun Deguchi, Kengo Nakata, Fumihiko Tachibana

Publikováno v: 2019 IEEE International Electron Devices Meeting (IEDM).

A lot of energy-efficient accelerators for inference has been reported. Our investigation result on dependence of energy efficiency on bit precision of accelerators shows that energy efficiency of in-memory/analog accelerators looks better than that

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::1d40555a743d5d3d3e738b2d76a0d868
https://doi.org/10.1109/iedm19573.2019.8993500

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Live Demonstration: FPGA-Based CNN Accelerator with Filter-Wise-Optimized Bit Precision

Autor: Daisuke Miyashita, Kengo Nakata, Tomoya Suzuki, Asuka Maki, Fumihiko Tachibana, Jun Deguchi

Publikováno v: ISCAS

To enhance the efficiency for inference of deep convolutional neural network without noticeable degradation of the recognition accuracy, we have proposed a filter-wise optimized quantization with variable bit precision. In addition, we have proposed

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::a3e3e3ab8f14a22b8fbd17377400bbb0
https://doi.org/10.1109/iscas.2019.8702208

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FPGA-based CNN Processor with Filter-Wise-Optimized Bit Precision

Autor: Kengo Nakata, Daisuke Miyashita, Jun Deguchi, Tomoya Suzuki, Asuka Maki, Fumihiko Tachibana

Publikováno v: A-SSCC

Many efforts have been made to improve the efficiency for inference of deep convolutional neural network. To achieve further improvement of the efficiency without penalty of accuracy, we propose filter-wise optimized quantization with variable precis

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::78c65e28160f4c8f29fa03136266fd7b
https://doi.org/10.1109/asscc.2018.8579342

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A 12.8 GB/S Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth and Large-Capacity Storage Systems

Autor: Jun Deguchi, Takashi Toi, Daisuke Miyashita, Yuta Tsubouchi, Makoto Morimoto, Yuji Satoh, Junii Wadatsumi, Fumihiko Tachibana

Publikováno v: VLSI Circuits

This paper proposes a prototype downlink I/F employing a tapered-BW daisy-chained topology enabled by a proposed SCM2 technique to exploit the low throughput of NAND I/O, which allows a NAND controller to handle 32 NAND PKGs on a single I/F channel.

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::2c2b38697142eadc86c7275afd407532
https://doi.org/10.1109/vlsic.2018.8502340

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A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers

Autor: Yuki Fujimura, Keiichi Kushida, Y. Takeyama, Fumihiko Tachibana, Tomoaki Yabe, Osamu Hirabayashi, A. Suzuki, Atsushi Kawasumi, Yusuke Niki

Publikováno v: IEEE Journal of Solid-State Circuits. 46:2545-2551

A digitized replica bitline delay technique has been proposed for random-variation-tolerant timing generation of static random access memory (SRAM) sense amplifiers (SA). The timing variation of SA attributable to the random variation of transistor t

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::30a2a7221f93accb1196e41228bf143c
https://doi.org/10.1109/jssc.2011.2164294

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A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit

Autor: Y. Takeyama, Shinichi Sasaki, Miyako Shizuno, Yusuke Niki, Fumihiko Tachibana, Atsushi Kawasumi, Keiichi Kushida, A. Suzuki, Yasuo Unekawa, Osamu Hirabayashi, Tomoaki Yabe

Publikováno v: ISSCC

This paper presents SRAM circuit techniques to reduce both active and standby mode power especially at room temperature (RT) where actual power consumption is dominant. A bit line power calculator is used to adaptively set the cell supply voltage (VC

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1746a7fd4107fb33385fcfa5e46aae5c
https://doi.org/10.1109/asscc.2013.6690973

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