Zobrazeno 1 - 10
of 12
pro vyhledávání: '"Fulvio Spagna"'
Autor:
Fulvio Spagna
Publikováno v:
Phase-Locked Frequency Generation and Clocking: Architectures and circuits for modern wireless and wireline systems ISBN: 9781785618857
With shrinking unit intervals (UI), the optimal horizontal centering of the reference sampling point becomes an important consideration for the choice of the phase detector and associated timing recovery method. Optimization of the timing recovery an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::84eb09db91246342daa81027eba72e05
https://doi.org/10.1049/pbcs064e_ch3
https://doi.org/10.1049/pbcs064e_ch3
Autor:
Syed Rubab, James Guthrie, Jing Wang, Clifford Ting, Ruslana Shulyzki, Aynaz Vatankhahghadim, Michael De Vita, Alireza Parsafar, Junhong Zhao, Noam Dolev, Sitaraman V. Iyer, Bahram Zand, Aleksey Tyshchenko, Mike Bichan, Eric Liu, Fulvio Spagna, Shaham Sharifian, Katya Tyshchenko
Publikováno v:
CICC
This paper presents the first SerDes design to demonstrate a PCI-Express 5 link with area of 0.33mm2 per lane, die edge usage per lane of 285 um, dynamic junction temperature range from -40C to 125C, energy efficiency of 11.4pJ/bit including PLL and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3c26acb0c936049f78d173528933a9ff
https://doi.org/10.1109/cicc48029.2020.9075947
https://doi.org/10.1109/cicc48029.2020.9075947
Autor:
Wenyan Jia, Fulvio Spagna, Rui Song, Dave Bradley, Lily Li, Amanda Tran, Shenggao Li, Michelle Wigton, Xiaoqing Wang, Luke Tong, Deepar Govindrajan, Meng-hung Chen, Chen Ji, Lee Eric M, Sujatha Gowder, Marcus Pasquarella, Matt Duwe, Frank Verdico, Sita Iyer, Michael De Vita, Roan M. Nicholson
Publikováno v:
A-SSCC
This paper presents a 2.5-16 Gbps Gen4 PCIe transceiver with 3-tap Tx EQ, and 8-tap Rx DFE in a 10nm FinFET CMOS technology. A low latency digital CDR is designed supporting a flexible timing recovery scheme. The CDR uses a 3-stage ring DCO, with a l
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::acafbcd450c1e5c17b902479592f09e0
https://doi.org/10.1109/asscc.2018.8579314
https://doi.org/10.1109/asscc.2018.8579314
Autor:
Fulvio Spagna
Publikováno v:
CICC
High-Speed Serial IO (HSIO) have, more than ever, become a critical ingredient in high performance communication systems. As the link data rate increases, the HSIO designer is tasked with optimizing Performance, Power Consumption, Reliability and Cos
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::57cacc41cb77b62a2ff7f661f158fa17
https://doi.org/10.1109/cicc.2018.8357111
https://doi.org/10.1109/cicc.2018.8357111
Autor:
Arvind Kumar, Zuoguo Wu, Fulvio Spagna, Sitaraman V. Iyer, Mohiuddin Mazumder, James E. Jaussi, Beomtaek Lee
Publikováno v:
ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems, MEMS and NEMS: Volume 1.
This paper describes an accurate and efficient analysis methodology that enables circuit optimization directly guided by platform-level metric such as link eye margin. Prior to this work, such analysis was not feasible due to significant compute time
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::390f4ca25587fcba63ff55ff5bb9521e
https://doi.org/10.1115/ipack2011-52279
https://doi.org/10.1115/ipack2011-52279
Publikováno v:
ITC
On-Die features available for validation and test on an integrated circuit play a major role in evaluating the performance of the functionality being realized by the circuit in a post-silicon environment and can considerably reduce time to market of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dba59292b2f8dda3a9651ed518591261
https://doi.org/10.1109/test.2010.5699242
https://doi.org/10.1109/test.2010.5699242
A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS
Autor:
Amanda Tran, Renuka Krishnamurthy, Luke Tong, Jeff Ou, Sitaraman V. Iyer, Xuguang Zhang, Kavitha Prasad, Sujatha Gowder, Doug Gambetta, Hendra Rustam, Yongping Fan, Mamatha Deshpande, John K. Wu, Ravindran Mohanavelu, Chien-chun Lin, Peter Kwok, Fulvio Spagna, Lidong Chen, Roan M. Nicholson, Marcus Pasquarella, Rohit Kumar
Publikováno v:
ISSCC
The last few years have witnessed a rapid increase in serial IO data rates as well as number of IO ports in microprocessors. This trend, poses significant challenges to the serial IO design because of area and power budget limitations but, above all,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::27154442da95010c83fb3f39bacd8a4e
https://doi.org/10.1109/isscc.2010.5433823
https://doi.org/10.1109/isscc.2010.5433823
Publikováno v:
2006 IEEE Asian Solid-State Circuits Conference.
This paper describes the design of a receiver that supports the operation from 1 to 4.25-Gb/s, enabling a single macro to satisfy different protocols. The receiver performs equalization to compensate for interconnect ISI, achieves 10 mV sensitivity a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::27579041cfd3ea27aa7fcac2cc8a09c4
https://doi.org/10.1109/asscc.2006.357933
https://doi.org/10.1109/asscc.2006.357933
Publikováno v:
1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.
With concentric data tracks separated radially by less than 10/spl mu/m, accurately detecting servo information on a magnetic disk is a crucial function of magnetic storage read channels. Valid servo Gray code confirms that the read/write head is in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b954458a94ee3c5c4beb7187ae9eac78
https://doi.org/10.1109/isscc.1997.585404
https://doi.org/10.1109/isscc.1997.585404
Autor:
Fulvio Spagna
Publikováno v:
ICECS
It is well known that time delays often cause instability in a closed-loop system forcing it to operate under sub-optimal conditions. Timing recovery systems encountered in today's communications systems are an example of such systems due to the late
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9315d7ee59ca317cb288bc7e92c020a0
https://doi.org/10.1109/icecs.2001.957475
https://doi.org/10.1109/icecs.2001.957475