Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Fu-Yi Tsai"'
Autor:
Fu-Yi Tsai, 蔡馥伊
102
The purpose of this study is to analyze the using of clustered classrooms in an open-space school, and analyze its team activities in teaching and learning. The research method includesliterature analysis, interviews and observation.The stud
The purpose of this study is to analyze the using of clustered classrooms in an open-space school, and analyze its team activities in teaching and learning. The research method includesliterature analysis, interviews and observation.The stud
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/89211916577182567594
Autor:
Fu-Yi Tsai, 蔡富義
89
In this dissertation, a simple in situ method is used to fabricate high-quality InGaAs/GaAs quantum dots on (111)B GaAs substrates. The formation of quantum dots was not due to strain relaxation, but due to the growth characteristics on (111)
In this dissertation, a simple in situ method is used to fabricate high-quality InGaAs/GaAs quantum dots on (111)B GaAs substrates. The formation of quantum dots was not due to strain relaxation, but due to the growth characteristics on (111)
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/01027384667376956015
Publikováno v:
2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.
The ESD robustness of gate-driven ESD clamp circuit in a 16-V CMOS process was investigated by the stresses of transmission line pulse (TLP), human-body-model ESD test, and machine-model (MM) ESD test. After TLP stresses of different voltage steps, t
Publikováno v:
Journal of the mechanical behavior of biomedical materials. 4(4)
In this study, the mechanical properties of bioactive coatings on Ti6Al4V substrates were investigated using instrumented nanoindentation. The aim was to observe the differences in the mechanical properties before and after immersion in collagen solu
Publikováno v:
ISCAS
A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit designed with the consideration of gate-leakage issue is proposed and verified in a 65-nm low-voltage CMOS process. The new proposed design has a very small leakage current of o
Publikováno v:
2009 IEEE International Reliability Physics Symposium.
A new power-rail ESD clamp circuit with ultra-low-leakage design is presented and verified in a 65-nm CMOS process with a leakage current of only 116nA at 25°C, which is much smaller than that (613μA) of traditional design. Moreover, it can achieve
Publikováno v:
2008 IEEE International Reliability Physics Symposium.
An electrical overstress failure induced by a latch-up test is studied in high-voltage integrated cricuits. The latchup test resulted in damage to the output NMOSFET due to snapbach and also resulted in a latch-up in the internal circuits. These mech
Autor:
Chen-Ti Hu, Fu-Yi Tsai
Publikováno v:
ECS Meeting Abstracts. :1426-1426
not Available.
Publikováno v:
2009 IEEE International Symposium on Circuits & Systems; 2009, p2281-2284, 4p
Publikováno v:
2009 IEEE International Reliability Physics Symposium; 2009, p750-753, 4p