Zobrazeno 1 - 10
of 22
pro vyhledávání: '"Front-side bus"'
Publikováno v:
2016 4th International Conference on Cyber and IT Service Management.
There processor FSB (Front Side Bus) and a multiplier that is used in setting the frequency of the processor. The FSB is the bus system is on line (bus) which physically connects the processor with the Northbridge chipset on the motherboard. This pat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a943d7847bba29cc9906d7b00f69e701
https://doi.org/10.1109/citsm.2016.7577467
https://doi.org/10.1109/citsm.2016.7577467
Publikováno v:
Computing in Science & Engineering. 12:78-83
Field-programmable gate arrays, which are more flexible than application-specific integrated circuits, have emerged as a low-power alternative to CPUs.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::864f7f3a665b9fb96276f66906ab40d7
https://doi.org/10.1109/mcse.2010.45
https://doi.org/10.1109/mcse.2010.45
Publikováno v:
IEEE Micro. 27:22-33
The Intel 5000 is a shared-memory, symmetric dual-processor system based on the energy-efficient, high-performance Intel core 2 dual- and quad-core processors. A key component is the northbridge, which interconnects processor, memory, and I/O interfa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ef1cc286ce9985a7a70b656d2076efd7
https://doi.org/10.1109/mm.2007.44
https://doi.org/10.1109/mm.2007.44
Publikováno v:
Journal of Physics: Conference Series. 898:082007
RapidIO (http://rapidio.org/) technology is a packet-switched high-performance fabric, which has been under active development since 1997. Originally meant to be a front side bus, it developed into a system level interconnect which is today used in a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::de15db85684cee6107324ae158d56640
https://doi.org/10.1088/1742-6596/898/8/082007
https://doi.org/10.1088/1742-6596/898/8/082007
Autor:
Richard Zhao
Publikováno v:
2014 15th International Conference on Electronic Packaging Technology.
Processor package has played significant role during Intel server's historic path. From the early front side bus (FSB) interconnect with north bridge chipset to the current quick path interconnect (QPI), server package architecture and design have me
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::81fcf8c18d25361718d236b9c4ea0a25
https://doi.org/10.1109/icept.2014.6922942
https://doi.org/10.1109/icept.2014.6922942
Publikováno v:
International Conference on Computer Networks and Information Technology.
There is always demand for high performance single chip microprocessor. In this regard microprocessor's manufacturers have worked hard and have gone through different techniques like increasing its clock speed, cache size, cores and hyper threading.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::43fa3fd08d2226c7f0962fecba338301
https://doi.org/10.1109/iccnit.2011.6020900
https://doi.org/10.1109/iccnit.2011.6020900
Publikováno v:
ISPASS
For higher processing and computing power, chip multiprocessors (CMPs) have become the new mainstream architecture. This shift to CMPs has created many challenges for fully utilizing the power of multiple execution cores. One of these challenges is m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5cc4013f09f0928845f20ef46a66d79f
https://doi.org/10.1109/ispass.2011.5762717
https://doi.org/10.1109/ispass.2011.5762717
Autor:
Tapan K. Sarkar, Yu Zhang
Publikováno v:
Parallel Solution of Integral Equation-Based EM Problems in the Frequency Domain
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::34ebee4518f22949d441910ae16b8ecb
https://doi.org/10.1002/9780470495094.ch5
https://doi.org/10.1002/9780470495094.ch5
Autor:
Li Zhao, Liang Wang, Ramesh Illikkal, Qigang Wang, Tao Wang, Lu Cao, John Du, Dong Liu, Kevin Wang, Michael Liao, Ravi Iyer
Publikováno v:
NAS
Larger last level caches are being considered for bridging the performance gap between the processors and the memory subsystem. It requires much longer simulation time to exercise the whole cache and get accurate evaluation results. In this paper, we
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5a932979065d0dbea00125226d7ce323
https://doi.org/10.1109/nas.2009.66
https://doi.org/10.1109/nas.2009.66
Autor:
Graham Schelle, Sebastian Steibl, Ralf Plate, Thorsten Mattner, Gautham N. Chinya, Franz Olbrich, Jamison D. Collins, Ronak Singhal, Perrry Wang, Hong Wang, Jim Brayton, Xiang Zou, Ethan Schuchman, Per Hammarlund
Publikováno v:
FPGA
We present an FPGA-synthesizable version of the Intel Atom processor core, synthesized to a Virtex-5 based FPGA emulation system. To make the production Atom design in SystemVerilog synthesizable through industry standard EDA tool flow, we transforme
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0dde4960f4d5c8bdb0b07404104b7a50
https://doi.org/10.1145/1508128.1508160
https://doi.org/10.1145/1508128.1508160