Zobrazeno 1 - 10
of 49
pro vyhledávání: '"Frederic Lazzarino"'
Autor:
Shreya Kundu, Stefan Decoster, Philippe Bezard, Ankit Nalin Mehta, Harold Dekkers, Frederic Lazzarino
Publikováno v:
ACS Applied Materials & Interfaces. 14:34029-34039
Publikováno v:
Japanese Journal of Applied Physics. 62:SI1004
Numerical data of two in situ optical acquisition systems were used in machine learning algorithm to evaluate an shallow trench isolation dry etch process in a dataset of more than 200 etched wafers processed during a year. Though overall recipe perf
Autor:
S. Paolillo, Guillaume Boccardi, N. Jourdan, Manoj Jaysankar, Zheng Tao, Sylvain Baudot, Geert Mannaert, Juergen Boemmels, T. Hopf, E. Capogreco, Shouhua Wang, Efrain Altamirano, E. Dupuy, Olalla Varela Pedreira, B. Briggs, Thomas Chiarella, Joris Cousserier, Sofie Mertens, Romain Ritzenthaler, Frank Holsteyns, C. Lorant, Goutham Arutchelvan, Ingrid Demonie, Steven Demuynck, K. Kenis, Xiuju Zhou, Anshul Gupta, F. Sebai, D. Radisic, Zsolt Tokei, Erik Rosseel, A. Sepulveda, Naoto Horiguchi, Christel Drijbooms, Antony Premkumar Peter, Haroen Debruyn, Nouredine Rassoul, Bilal Chehab, P. Morin, Boon Teik Chan, Christopher J. Wilson, Katia Devriendt, Noemie Bontemps, Frederic Lazzarino, Paola Favia, Lieve Teugels, D. Yakimets, F. Schleicher, Houman Zahedmanesh, Jerome Mitard, Min-Soo Kim, An De Keersgieter, Sujith Subramanian, Kevin Vandersmissen, Hans Mertens, Eugenio Dentoni Litta, Yong Kong Siew
Publikováno v:
IEEE Transactions on Electron Devices. 67:5349-5354
Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5-nm node. This work demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. BPR technology requires insertion of metal in the front-e
Autor:
Prem Panneerchelvam, Ankur Agarwal, Chad M. Huard, Alessandro Vaglio Pret, Antonio Mani, Roel Gronheid, Marc Demand, Kaushik Kumar, Sara Paolillo, Frederic Lazzarino
Publikováno v:
Journal of Vacuum Science & Technology B. 40:062601
Quantitatively accurate, physics-based, computational modeling of etching and lithography processes is essential for modern semiconductor manufacturing. This paper presents lithography and etch models for a trilayer process in a back end of the line
Autor:
Zaid El-Mekki, F. Schleicher, Frederic Lazzarino, D. Trivkovic, Zsolt Tokei, B. De-Wachter, S. V. Gompel, L. Halipre, E. Vancoille, S. Decoster, G. Muroch, Thomas Witters, L. Dupas, O. Varela-Pereira, B. Briggs, Quoc Toan Le, Harinarayanan Puliyalil, Christopher J. Wilson, Philippe Leray, N. Jourdan, I. Demonie, C. Lorant, Joost Bekaert, Nancy Heylen, Y. Kimura, Rogier Baert, M. H. van der Veen, J. Versluijs, Miroslav Cupak, Patrick Verdonck, K. Croes, Manoj Jaysankar, Anne-Laure Charley, J. Heijlen, J. Uk-Lee, Ivan Ciofi, Y. Drissi, V. Vega-Gonzalez, S. Paolillo, H. Vats, D. Montero, L. Rynders, Els Kesters, M. Ercken, A. Lesniewska, R. Kim, Lieve Teugels, T. Webers
Publikováno v:
2020 IEEE International Electron Devices Meeting (IEDM).
The integration of high-aspect-ratio (AR) supervias (SV) into a 3 nm node test vehicle, bypassing an intermediate 21 nm pitch layer, is demonstrated. Place-and-route (PnR) simulations of the Power Delivery Network (PDN) proved IR-drop reduction with
Autor:
P. Morin, Julien Ryckaert, Doyoung Jang, Lieve Teugels, Efrain Altamirano-Sanchez, M. H. Na, Jürgen Bömmels, F. Schleicher, S. Wang, A. Sepúlveda, Serge Biesemans, C. Lorant, I. Demonie, Gayle Murdoch, E. Dentoni Litta, A. Lesniewska, Zsolt Tokei, Bilal Chehab, Farid Sebaai, Antony Premkumar Peter, N. Nagesh, Naoto Horiguchi, Frederic Lazzarino, Boon Teik Chan, Geert Hellings, O. Varela Pedreira, N. Jourdan, D. Radisic, O. Richard, Z. Tao, Hans Mertens, P. Marien, Anshul Gupta, Nancy Heylen, Steven Demuynck, Katia Devriendt
Publikováno v:
2020 IEEE International Electron Devices Meeting (IEDM).
This paper reports BPR/Via-to-BPR (VBPR) module development at 24nm fin pitch (FP) / 42nm contacted gate pitch (CPP), and W and Ru-BPR and Ru- Contact-to-Active (M0A)/VBPR resistance (R) & electromigration (EM). BPR dielectric barrier, BPR plug barri
Autor:
Nancy Heylen, K. Croes, Rogier Baert, S. Park, Geoffrey Pourtois, Jean-Philippe Soulie, Katia Devriendt, Christopher J. Wilson, Ming Mao, Q-T. Le, V. Blanco, Gayle Murdoch, Herbert Struyf, Anshul Gupta, V. Vega, Lieve Teugels, S. Paolillo, N. Jourdan, Kiroubanand Sankaran, J. Sweerts, Ivan Ciofi, S. Decoster, P. Morin, Els Kesters, Juergen Boemmels, Frederic Lazzarino, Zs. Tokei, Christoph Adelmann, M. H. van der Veen, M. Ercken, Kris Vanstreels, S. Van Elshocht, M. O'Toole, J. Versluijs, M. H. Na, Frank Holsteyns, Houman Zahedmanesh
Publikováno v:
2020 IEEE International Electron Devices Meeting (IEDM).
Interconnect options will be introduced and reviewed targeting tight pitch metal layers at the local levels. Examples include hybrid metallization, semi-damascene interconnects as well as potential new conductor materials.
Autor:
Danny Wan, Sebastien Couet, Xiaoyu Pao, Laurent Souriau, Diana Tsvetanova, Diziana Vangoidsenhoven, Arame Thiam, Antoine Pacco, Anton Potocnik, Massimo Mongillo, Tsvetan Ivanov, Julien Jussot, Jeroen Verjauw, Rohith Acharya, Jeroen Heijlen, GabrieleLuca Donadio, Bogdan Govoreanu, Frederic Lazzarino, Iuliana Radu
Publikováno v:
Extended Abstracts of the 2020 International Conference on Solid State Devices and Materials.
Autor:
Anne-Laure Charley, Philippe Leray, Christophe Beral, Romuald Blanc, Amir-Hossein Tamaddon, Poulomi Das, Werner Gillijns, Ataklti Weldeslassie, Frederic Lazzarino
Publikováno v:
Extreme Ultraviolet Lithography 2020.
The key challenge to enable a good defectivity control for extreme ultraviolet (EUV) single expose at 32nm pitch is to understand what are the main drivers for defect generation. CD is one of the main contributors, and has many sources of variability
Autor:
Tao Zheng, Frederic Lazzarino, Efrain Altamirano-Sánchez, Zhang Liping, Boon Teik Chan, Emmanuel Dupuy
Publikováno v:
Advanced Etch Technology for Nanopatterning IX.
FinFETs have demonstrated significant performance improvement compared to planar devices, because of its superior short channel control and higher driving capability at a much smaller footprint. It has become the mainstream technology in CMOS industr