Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Franklin M. Baez"'
Autor:
Benjamin V. Fasano, Richard F. Indyk, Brittany Hedrick, Franklin M. Baez, Jorge Lubguban, Michael S. Cranmer, Shidong Li, Luc Guerin, Sarah H. Knickerbocker, David J. Lewison, Marc Phaneuf Luc Ouellet, Ian D. Melville, Koushik Ramachandran, Charles L. Arvin, Maryse Cournoyer, Daniel Berger, Christopher L. Tessler, John J. Garant, Matthew Angyal, Jean Audet, Vijay Sukumaran, Subramanian S. Iyer
Publikováno v:
2016 IEEE 66th Electronic Components and Technology Conference (ECTC).
The processes key to enabling 3D manufacturing, namely, bond, backgrind, and through silicon via (TSV) reveal, are extended for 300 mm glass substrates to fabricate a heterogeneous, multi-die, 2.5D glass interposer. Based on an existing silicon inter
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b2b4aad595f4909b659aff313054dc4c
https://doi.org/10.1109/ectc.2016.261
https://doi.org/10.1109/ectc.2016.261
Publikováno v:
Journal of Circuits, Systems and Computers. 11:231-245
A strategy to enhance the speed and power characteristics of an industrial circuit is demonstrated in this paper. It is shown that nonzero clock skew scheduling can improve circuit performance while relaxing the strict timing constraints of the criti
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7240df3ea9cc151da01f9c5b584a3043
https://doi.org/10.1142/s0218126602000410
https://doi.org/10.1142/s0218126602000410
Autor:
Christopher N. Collins, Ed Sprogis, Mike Cranmer, Daniel Berger, Franklin M. Baez, Michael J. Shapiro, Jean Audet, Subramania S. Iyer
Publikováno v:
2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems.
A multichip module package has been designed in IBM's silicon technology. The module consists of two chips of same size and type communicating horizontally through a silicon interposer to a large ASIC chip. The chip to chip links operate at 8 Gbps wi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b359ad39a792e93b4132849f45a3e332
https://doi.org/10.1109/epeps.2012.6457902
https://doi.org/10.1109/epeps.2012.6457902
Publikováno v:
19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems.
Ceramic packages for high performance server processors have many wiring layers and via count due to the large number of input-output (I/Os) needed in high end computers to attain performance targets. Good AC operation of the interconnect is critical
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fa3e18fbf7603742a9a076f07bff4fb3
https://doi.org/10.1109/epeps.2010.5642792
https://doi.org/10.1109/epeps.2010.5642792
Publikováno v:
2008 IEEE-EPEP Electrical Performance of Electronic Packaging.
High performance glass ceramic (HPGC) packages widely used in various range of IBM server applications are characterized for high frequency performance of SerDes differential links using TDR and network analyzer measurements and their design to perfo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e1682f680f7396639cf438ff6794b223
https://doi.org/10.1109/epep.2008.4675925
https://doi.org/10.1109/epep.2008.4675925
Publikováno v:
2007 IEEE Electrical Performance of Electronic Packaging.
We describe a methodology to route differential pairs in vertical layers in a high performance multi-chip module ceramic package. By matching the impedance of these vertical differential pairs to their conventional counterparts and adopting a power d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2e78de4e387766218e8660a24094bf72
https://doi.org/10.1109/epep.2007.4387167
https://doi.org/10.1109/epep.2007.4387167
Publikováno v:
Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558).
On-chip power dissipation has become a fundamental design issue in high performance integrated circuits. A technique to significantly reduce the power dissipated in the non-critical data paths of an industrial circuit is demonstrated. The application
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::250cd4d3732494dfdfec43bed49ac50f
https://doi.org/10.1109/asic.2001.954668
https://doi.org/10.1109/asic.2001.954668
Publikováno v:
ICECS
A demonstration of the application of non-zero clock skew scheduling to enhance the speed characteristics of several functional unit blocks in a high performance processor is presented. It is shown that non-zero clock skew scheduling can improve circ
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a8e8e1b1c27cdd52ce1e8e327c33b3d0
https://doi.org/10.1109/icecs.2001.957650
https://doi.org/10.1109/icecs.2001.957650
Publikováno v:
DAC
Power consumption has become one of the biggest challenges in high-performance microprocessor design. The rapid increase in the complexity and speed of each new CPU generation is outstripping the benefits of voltage reduction and feature size scaling
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::10260d967e92030089090f30157cc06e
https://doi.org/10.1145/277044.277227
https://doi.org/10.1145/277044.277227