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Plasma Dicing Process-Flows for Advanced Packaging Fabrications

Autor: Sando Hideyuki, Frank Wei, Tomotaka Tabuchi

Publikováno v: International Symposium on Microelectronics. 2017:000215-000223

Comprehensive investigations were conducted on identifying integration efforts needed to adapt plasma dicing technology in BEOL pre-production environments. First, the authors identified a few suitable process flows. Within the plasma dicing process

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::2a94e69c9a5ed79bfe365aafc1d18f66
https://doi.org/10.4071/isom-2017-wa31_102

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Embedded Trench Redistribution Layers at 2– $5~\mu \text{m}$ Width and Space by Excimer Laser Ablation and Surface Planer Processes for 20– $40~\mu \text{m}$ I/O Pitch Interposers

Autor: Habib Hichri, Yuya Suzuki, Venky Sundaram, Rao Tummala, Frank Wei

Publikováno v: IEEE Transactions on Components, Packaging and Manufacturing Technology. 7:838-845

This paper reports on one of the first demonstrations of the formation and metallization of 2–5- $\mu \text{m}$ lines and spaces by an embedded trench method in two dry-film polymer dielectrics, Ajinomoto build-up film and preimidized polyimide, wi

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::cd3ef85864677ffba440d01f7831223a
https://doi.org/10.1109/tcpmt.2017.2676023

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MLPerf Inference Benchmark

Publikováno v: ISCA

Machine-learning (ML) hardware and software system demand is burgeoning. Driven by ML applications, the number of different ML inference systems has exploded. Over 100 organizations are building ML inference chips, and the systems that incorporate ex

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7a2417894de20d08d29ba667a4080f9a

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First Demonstration of Silicon-Like >250 I/O Per mm Per Layer Multilayer RDL on Glass Panel Interposers by Embedded Photo-Trench and Fly Cut Planarization

Autor: Fuhan Liu, Atsushi Kubo, Rao Tummala, Bartlet H. DeProspo, Frank Wei, Ye Chen, Venkatesh Sundaram, Chandrasekharan Nair

Publikováno v: 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

This paper demonstrates for the first time >250 I/O per mm per layer on glass panels utilizing embedded photo-trench and fly cut planarization processes to meet the demands of next generation high bandwidth 2.5D Interposers. This paper combines the u

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::8fce62385b210592b8d4888799e1f5a3
https://doi.org/10.1109/ectc.2018.00177

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Embedded Trench Redistribution Layers (RDL) by Excimer Laser Ablation and Surface Planer Processes

Autor: Lee Seongkuk, Ye Chen, Ognian N. Dimov, Rao Tummala, Habib Hichri, Markus Arendt, Yuya Suzuki, Deepak Arora, Sanjay Malik, Kwon Sang Lee, Frank Wei, Venky Sundaram

Publikováno v: 2017 IEEE 67th Electronic Components and Technology Conference (ECTC).

This paper reports the demonstration of 2-5 µm embedded trench formation in dry film polymer dielectrics such as Ajinomoto build-up film (ABF) and Polyimide without using chemical mechanical polishing (CMP) process. The trenches in these dielectrics

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::3d652513cf613bb7060eadb306c35991
https://doi.org/10.1109/ectc.2017.15

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First Demonstration of Panel Glass Fan-Out (GFO) Packages for High I/O Density and High Frequency Multi-chip Integration

Autor: Cody Lee, Lutz Parthier, Yoichiro Sato, Rao Tummala, Chintan Buch, Venky Sundaram, Vanessa Smet, Frank Wei, Tailong Shi

Publikováno v: 2017 IEEE 67th Electronic Components and Technology Conference (ECTC).

Ultra-thin, panel-level glass fan-out packages (GFO) were demonstrated for next-generation fan-out packaging with high-density high-performance digital, analog, power, RF and mm-wave applications. The key advances with GFO include: 1) large area pane

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::c1169e8a2324de4e7f1ad8b34da88dc9
https://doi.org/10.1109/ectc.2017.287

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Enabling Chip-to-Substrate All-Cu Interconnections: Design of Engineered Bonding Interfaces for Improved Manufacturability and Low-Temperature Bonding

Autor: Vanessa Smet, Gustavo Ramos, Kashyap Mohan, Ninad Shahane, Frank Wei, Rao Tummala, Arnd Kilian, Antonia Antoniou, Pulugurtha Markondeya Raj, Robin Taylor

Publikováno v: 2017 IEEE 67th Electronic Components and Technology Conference (ECTC).

This paper presents the design and implementation of engineered nanoscale bonding interfaces as an effective strategy to improve manufacturability of Cu-Cu bonding to the level where it can, for the first time, be applied to chip-to-substrate (C2S) a

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::e5bb3a5ca36473956b6a095dd34e7a99
https://doi.org/10.1109/ectc.2017.313

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Advancements in Phenomenological Understanding of Thinning and Planarization Processes for TSV-Enabled 2.5-3D Device Fabrications

Autor: Frank Wei

Publikováno v: International Symposium on Microelectronics. 2014:000708-000712

Innovations and novel development in substrate thinning and planarization processes driven by advanced packages fabrications are surveyed. For direct 3D die-stacking process approach, a novel methodology for bonded wafer grinding has been put in plac

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::10117e860922cd207d118691f15bdb0c
https://doi.org/10.4071/isom-wp41

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