Zobrazeno 1 - 10
of 25
pro vyhledávání: '"Frank E. Gennari"'
Autor:
Jonathan Fales, Binod Kumar G. Nair, Jeffrey E. Nelson, Frank E. Gennari, Philippe Hurat, Jac Condella, Akif Sultan, Aaron Sinnott, Xiaoyuan Qi, Sriram Madhavan, Uwe Paul Schroeder, Rwik Sengupta, Ya-Chieh Lai
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 34:372-378
A novel foundry yield model for integrated circuit products has been developed based on critical area scaling. The newly proposed model does not need the information of the defect density by failure mode. This has considerably simplified the model in
Autor:
Philippe Hurat, Ya-Chieh Lai, Atul Chittora, Jeffrey E. Nelson, Xiaoyuan Qi, Rwik Sengupta, Binod Kumar G. Nair, Aaron Sinnott, Frank E. Gennari, Jac Condella, Jonathan Fales, Shobhit Malik
Publikováno v:
Design-Process-Technology Co-optimization XV.
Systematic defects have drawn a lot of focus from the semiconductor industry, especially in the technology development and early technology ramp. However, random defects are still dominant when the technology is mature and in highvolume manufacturing
Autor:
Frank E. Gennari, Piyush Pathak, Ya-Chieh Lai, Sangah Lee, Jae-Hyun Kang, Jac Condella, Joong-Won Jeon, Jin Kim, Philippe Hurat, Jaehwan Kim, Shin Byung-Chul
Publikováno v:
Design-Process-Technology Co-optimization for Manufacturability XIV.
Process and reliability risks have become critically important during mass production at advanced technology nodes even with Extreme Ultraviolet Lithography (EUV) illumination. In this work, we propose a design-for-manufacturability solution using a
Publikováno v:
DAC
VLSI layout patterns provide critic resources in various design for manufacturability researches, from early technology node development to back-end design and sign-off flows. However, a diverse layout pattern library is not always available due to l
Autor:
Piyush Pathak, Jin Kim, Junsu Jeon, Jaehwan Kim, Byung-Moo Kim, Ya-Chieh Lai, Jae-Hyun Kang, Sangah Lee, Frank E. Gennari, Philippe Hurat, Shin Byung-Chul, Seung Weon Paek
Publikováno v:
Design-Process-Technology Co-optimization for Manufacturability XIII.
Continuous scaling of CMOS process technology to 7nm (and below) has introduced new constraints and challenges in determining Design-for-Yield (DFY) solutions. In this work, traditional solutions such as improvements in redundancy and in compensating
Publikováno v:
Design-Process-Technology Co-optimization for Manufacturability XIII.
Design-process weakpoints also known as hotspots cause systematic yield loss in semiconductor manufacturing. One of the main goals of DFM is to detect such hotspots. For the application of AI in hotspot detection, a variety of machine learning-based
Autor:
Piyush Pathak, Frank E. Gennari, Moutaz Fakhry, Ya-Chieh Lai, Abdullah Yassine, Jeffrey E. Nelson, Jason P. Cain
Publikováno v:
Design-Process-Technology Co-optimization for Manufacturability XIII.
Layout-pattern-based approaches for physical design analysis and verification have become mainstream in recent years and are enabling many new applications. Prior work introduced the ability to collect all patterns from multiple layouts into a catalo
Publikováno v:
ASP-DAC
Layout hotpot detection is one of the critical steps in modern integrated circuit design flow. It aims to find potential weak points in layouts before feeding them into manufacturing stage. Rapid development of machine learning has made it a preferab
Machine learning-based lithography hotspot detection has been deeply studied recently, from varies feature extraction techniques to efficient learning models. It has been observed that such machine learning-based frameworks are providing satisfactory
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::384d35d8d09d09a20470684766152299
Publikováno v:
Design-Process-Technology Co-optimization for Manufacturability XII.
Building on previous work for cataloging unique topological patterns in an integrated circuit physical design, a new process is defined in which a risk scoring methodology is used to rank patterns based on manufacturing risk. Patterns with high risk