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of 6
pro vyhledávání: '"Francis Patrick O'Connell"'
Autor:
Pradip Bose, Roberto Gioiosa, Victor Jimenez, Francis Patrick O'Connell, Francisco J. Cazorla, Bruce Mealey, Alper Buyuktosunoglu
Publikováno v:
ACM Transactions on Parallel Computing. 1:1-25
Hardware data prefetch engines are integral parts of many general purpose server-class microprocessors in the field today. Some prefetch engines allow users to change some of their parameters. But, the prefetcher is usually enabled in a default confi
Autor:
Michael Thomas Vaden, Hung Qui Le, Francis Patrick O'Connell, Wolfram Sauer, D. Q. Nguyen, B. J. Ronchetti, Eric M. Schwarz, William J. Starke, J. S. Fields
Publikováno v:
IBM Journal of Research and Development. 51:639-662
This paper describes the implementation of the IBM POWER6™ microprocessor, a two-way simultaneous multithreaded (SMT) dual-core chip whose key features include binary compatibility with IBM POWER5™ microprocessor-based systems; increased function
Autor:
Pradip Bose, Francisco J. Cazorla, Alper Buyuktosunoglu, Francis Patrick O'Connell, Mateo Valero, Victor Jimenez
Publikováno v:
HPCA
Recercat. Dipósit de la Recerca de Catalunya
instname
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
instname
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Memory bandwidth is a crucial resource in computing systems. Current CMP/SMT processors have a significant number of cores and they can run many threads concurrently. This large thread count adds high pressure to the memory bus, which demands high ba
Autor:
S. W. White, Francis Patrick O'Connell
Publikováno v:
IBM Journal of Research and Development. 44:873-884
The POWER3 processor is a high-performance microprocessor which excels at technical computing. Designed by IBM and deployed in various IBM RS/6000® systems, the superscalar RISC POWER3 processor boasts many advanced features which give it exceptiona
Publikováno v:
Journal of Systems Architecture. 45:1111-1137
We consider the floating point microarchitecture support in RISC superscalar processors. We briefly review the fundamental performance trade-offs in the design of such microarchitecutres. We propose a simple, yet effective bounds model to deduce the
Autor:
Francisco J. Cazorla, Pradip Bose, Alper Buyuktosunoglu, Roberto Gioiosa, Victor Jimenez, Francis Patrick O'Connell
Publikováno v:
PACT
Hardware data prefetch engines are integral parts of many general purpose server-class microprocessors in the field today. Some prefetch engines allow the user to change some of their parameters. The prefetcher, however, is usually enabled in a defau