Zobrazeno 1 - 10
of 37
pro vyhledávání: '"Florian Brandner"'
Autor:
Camille Noûs, Florian Brandner
Publikováno v:
Real-Time Systems. 58:36-84
Bounding the Worst-Case Execution Time (WCET) of real-time software requires precise knowledge about the reachable program and hardware states that might be observed at runtime. The analysis of precise cache states is particularly important and chall
Publikováno v:
RTNS 2022: The 30th International Conference on Real-Time Networks and Systems
RTNS 2022: The 30th International Conference on Real-Time Networks and Systems, Jun 2022, Paris France, France. pp.140-150, ⟨10.1145/3534879.3534907⟩
RTNS 2022: The 30th International Conference on Real-Time Networks and Systems, Jun 2022, Paris France, France. pp.140-150, ⟨10.1145/3534879.3534907⟩
International audience
Publikováno v:
International Journal on Software Tools for Technology Transfer
International Journal on Software Tools for Technology Transfer, 2022, 24 (3), pp.415-440. ⟨10.1007/s10009-022-00655-1⟩
International Journal on Software Tools for Technology Transfer, 2022, 24 (3), pp.415-440. ⟨10.1007/s10009-022-00655-1⟩
International audience
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::083f33e98aba9e11deb3616f59abb0f5
https://telecom-paris.hal.science/hal-03702426
https://telecom-paris.hal.science/hal-03702426
Publikováno v:
RTCSA
Correctness is an important concern during the development of real-time systems. In addition to the functional correctness, the timing behavior is often formally verified in order to ensure that correct results are delivered in-time for all possible
Autor:
Florian Brandner, Diego Novillo
Publikováno v:
SSA-based Compiler Design ISBN: 9783030805142
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d45123d096e6f899fc57c4bbf176ed20
https://doi.org/10.1007/978-3-030-80515-9_8
https://doi.org/10.1007/978-3-030-80515-9_8
Publikováno v:
Real-Time Systems
Real-Time Systems, Springer Verlag, 2019, ⟨10.1007/s11241-019-09336-w⟩
Real-Time Systems, 2019, ⟨10.1007/s11241-019-09336-w⟩
Real-Time Systems, Springer Verlag, 2019, ⟨10.1007/s11241-019-09336-w⟩
Real-Time Systems, 2019, ⟨10.1007/s11241-019-09336-w⟩
Multi-core architectures pose many challenges in real-time systems, which arise from contention between concurrent accesses to shared memory. Among the available memory arbitration policies, time-division multiplexing (TDM) ensures a predictable beha
Autor:
Florian Brandner, Camille Noûs
Publikováno v:
RTNS
RTNS 2020: 28th International Conference on Real-Time Networks and Systems
RTNS 2020: 28th International Conference on Real-Time Networks and Systems, Jun 2020, Paris France, France. pp.44-55, ⟨10.1145/3394810.3394811⟩
RTNS 2020: 28th International Conference on Real-Time Networks and Systems
RTNS 2020: 28th International Conference on Real-Time Networks and Systems, Jun 2020, Paris France, France. pp.44-55, ⟨10.1145/3394810.3394811⟩
Bounding the Worst-Case Execution Time (WCET) of real-time software requires precise knowledge about the reachable program and hardware states that might be observed at runtime. The analysis of precise cache states is particularly important and chall
Publikováno v:
RTSS 2018-IEEE Real-Time Systems Symposium
RTSS 2018-IEEE Real-Time Systems Symposium, Dec 2018, Nashville, France. pp.456-468, ⟨10.1109/RTSS.2018.00059⟩
RTSS
RTSS 2018-IEEE Real-Time Systems Symposium, Dec 2018, Nashville, France. pp.456-468, ⟨10.1109/RTSS.2018.00059⟩
RTSS
International audience; Multi-core architectures pose many challenges in real-time systems, which arise from contention between concurrent accesses to shared memory. Among the available memory arbitration policies, Time Division Multiplexing (TDM) en
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1bccc38722247d3a24204b17089f616a
https://hal.archives-ouvertes.fr/hal-01994629
https://hal.archives-ouvertes.fr/hal-01994629
Publikováno v:
Real-Time Systems
Real-Time Systems, Springer Verlag, 2018, ⟨10.1007/s11241-018-9298-7⟩
Real-Time Systems, 2018, ⟨10.1007/s11241-018-9298-7⟩
Naji, A, Abbaspour, S, Brandner, F & Jan, M 2018, ' Analysis of preemption costs for the stack cache ', Real-Time Systems, vol. 54, no. 3, pp. 700–744 . https://doi.org/10.1007/s11241-018-9298-7
Real-Time Systems, Springer Verlag, 2018, ⟨10.1007/s11241-018-9298-7⟩
Real-Time Systems, 2018, ⟨10.1007/s11241-018-9298-7⟩
Naji, A, Abbaspour, S, Brandner, F & Jan, M 2018, ' Analysis of preemption costs for the stack cache ', Real-Time Systems, vol. 54, no. 3, pp. 700–744 . https://doi.org/10.1007/s11241-018-9298-7
International audience; The design of tailored hardware has proven a successful strategy to reduce the timing analysis overhead for (hard) real-time systems. The stack cache is an example of such a design that was shown to provide good average-case p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f6d384a10d30f84ac376f1ec5a897cef
https://hal-cea.archives-ouvertes.fr/cea-01773654/file/naji2018.pdf
https://hal-cea.archives-ouvertes.fr/cea-01773654/file/naji2018.pdf
Publikováno v:
WCSP
This article summarizes our current studies aiming at a better understanding of the energy consumption of a microprocessor during the execution of an application through a combination of theoretical results and experimental validations, The analysis