Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Flavio M. De Paula"'
Publikováno v:
Innovations in Systems and Software Engineering. 15:191-206
Verification coverage is an important metric in any hardware verification effort. Coverage models are proposed as a set of events the hardware may exhibit, intended to be possible under a test scenario. At the system level, these events each correspo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b3ba9e37cc669563bb75c583ac4aaeb4
https://doi.org/10.1007/s11334-019-00348-0
https://doi.org/10.1007/s11334-019-00348-0
Publikováno v:
DAC
We present a method for selecting trace messages for post-silicon validation of Systems-on-a-Chips (SoCs) with diverse usage scenarios. We model specifications of interacting flows in typical applications. Our method optimizes trace buffer utilizatio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7f40efa46cc2accff91e8b8922beee86
https://doi.org/10.1109/dac.2018.8465839
https://doi.org/10.1109/dac.2018.8465839
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783319779348
NFM
NFM
Verification coverage is an important metric in any hardware verification effort. Coverage models are proposed as a set of events the hardware may exhibit, intended to be possible under a test scenario. At the system level, these events each correspo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e836e86fbef3295b2f9a027a6440a689
https://doi.org/10.1007/978-3-319-77935-5_7
https://doi.org/10.1007/978-3-319-77935-5_7
Autor:
Pedro J.M. Patricio, Flavio M. De Paula, Aldo J. Peixoto, David Dorigo, Luciano V. Pinto, Sergio F.F. Santos
Publikováno v:
Kidney International. 66:1232-1238
Clinical consequences of an individualized dialysate sodium prescription in hemodialysis patients.BackgroundPredialysis plasma sodium (Na+) concentration is relatively constant in hemodialysis (HD) patients, and a higher dialysate Na+ concentration c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d5931e8e9464abcb460722a178c4659b
https://doi.org/10.1111/j.1523-1755.2004.00876.x
https://doi.org/10.1111/j.1523-1755.2004.00876.x
Publikováno v:
Computer Aided Verification ISBN: 9783642314230
CAV
CAV
A primary challenge in post-silicon debug is the lack of observability of on-chip signals. In 2008, we introduced BackSpace, a new paradigm that uses repeated silicon runs to automatically compute debug traces that lead to an observed buggy state. Th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2c9ffb427372b7e39ff08983572858c8
https://doi.org/10.1007/978-3-642-31424-7_37
https://doi.org/10.1007/978-3-642-31424-7_37
Publikováno v:
DAC
This paper presents TAB-BackSpace, our novel scheme to provide the effect of an unlimited-length trace buffer with no on-chip overhead beyond the existing debug logic. We present the theoretical foundation of our work, simulation studies on how we re
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a575f3d24263fef995381d48a272e3e8
https://doi.org/10.1145/2024724.2024821
https://doi.org/10.1145/2024724.2024821
Publikováno v:
2010 Ninth International Workshop on Parallel and Distributed Methods in Verification, and Second International Workshop on High Performance Computational Systems Biology.
We present Preach, an industrial strength distributed explicit state model checker based on Murphi. The goal of this project was to develop a reliable, easy to maintain, scalable model checker that was compatible with the Murphi specification languag
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ea62a33775abdcb9deed469524492268
https://doi.org/10.1109/pdmc-hibi.2010.13
https://doi.org/10.1109/pdmc-hibi.2010.13
Autor:
Flavio M. De Paula, Alan J. Hu
Publikováno v:
2007 44th ACM/IEEE Design Automation Conference.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c24a771a377b107c1bfa4e0219ede7e7
https://doi.org/10.1109/dac.2007.375126
https://doi.org/10.1109/dac.2007.375126
Autor:
Jose Augusto M. Nacif, Harry Foster, Edjard Mota, A.O. Fernandes, Flavio M. de Paula, Claudionor Coelho, Márcia Roberta Falcão Mota
Publikováno v:
IFIP International Federation for Information Processing ISBN: 9780387334028
VLSI-SoC (Selected Papers)
VLSI-SoC (Selected Papers)
White-box verification is a technique that reduces observability problems by locating a failure during design simulation without the need to propagate the failure to the I/O pins. White-box verification in chip level designs can be implemented using
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eff9a878b9bdd254d3898d7f3b00f796
https://doi.org/10.1007/0-387-33403-3_7
https://doi.org/10.1007/0-387-33403-3_7