3D interconnect architecture for high-bandwidth massively paralleled imager

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What Patent Applications Reveal.

Autor: Neuhaus, H. J., Fillion, R. A., Bauer, C. E.

Publikováno v: SMT: Surface Mount Technology. Aug2010, Vol. 25 Issue 4, p32-42. 8p.

Embedded Chip Build-Up Using Fine Line Interconnect.

Autor: Fillion, R., Woychik, C., Tan Zhang, Bitting, D.

Publikováno v: 2007 Proceedings 57th Electronic Components & Technology Conference; 2007, p49-53, 5p

Packaging of devices for topside cooling by replacing air-bridges with Su-8 polymer bridges [MESFET example].

Autor: Wright, J.I., Fillion, R., Meyer, L., Shaddock, D.

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A silicon-carbide micro-capillary pumped loop for cooling high power devices.

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