Zobrazeno 1 - 10
of 26
pro vyhledávání: '"Filippo Schembari"'
Autor:
Ali Esmailiyan, Jianglin Du, Teerachot Siriburanon, Filippo Schembari, Robert Bogdan Staszewski
Publikováno v:
IEEE Open Journal of Circuits and Systems, Vol 2, Pp 23-31 (2021)
This article demonstrates a digitally friendly time-based analog-to-digital converter (ADC) exploiting Dickson charge-pump (CP) as part of a voltage-to-time conversion (VTC) implemented in 28-nm CMOS. In the proposed technique, the Dickson CP generat
Externí odkaz:
https://doaj.org/article/1f1a19608ccc40bd88685a6bb0352dd8
Autor:
Mojtaba Bagheri, Filippo Schembari, Hashem Zare-Hoseini, Robert Bogdan Staszewski, Arokia Nathan
Publikováno v:
IEEE Open Journal of Circuits and Systems, Vol 2, Pp 420-433 (2021)
Interleaving is a powerful technique that boosts the speed of an ADC. The power efficiency of such a technique is mainly affected by the overhead of the circuitry used to mitigate the impact of inter-channel mismatches on the ADC’s performance. Thi
Externí odkaz:
https://doaj.org/article/cf543903dade44f2bfbabc333aae9700
Exploring Speed Maximization of Frequency-to-Digital Conversion for Ultra-Low-Voltage VCO-Based ADCs
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 70:1043-1056
Publikováno v:
IEEE Journal of Solid-State Circuits. 57:1684-1699
This article demonstrates the potential of deep-subthreshold mixed-signal circuits in delivering medium-to-high performance to supply-constrained, energy-harvesting Internet of Things (IoT) sensing applications. This effort encapsulates the design an
Autor:
Robert Bogdan Staszewski, Ali Esmailiyan, Filippo Schembari, Teerachot Siriburanon, Jianglin Du
Publikováno v:
IEEE Open Journal of Circuits and Systems, Vol 2, Pp 23-31 (2021)
This article demonstrates a digitally friendly time-based analog-to-digital converter (ADC) exploiting Dickson charge-pump (CP) as part of a voltage-to-time conversion (VTC) implemented in 28-nm CMOS. In the proposed technique, the Dickson CP generat
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 67:2828-2832
This brief introduces an adaptive-resolution (AR) quasi-level-crossing delta modulator ADC with a voltage-controlled oscillator (VCO)-based residue quantizer for Internet-of-Things (IoT) wireless sensor nodes. The residue voltage signal is digitized
Autor:
Mojtaba Bagheri, Filippo Schembari, Robert Bogdan Staszewski, Naser Pourmousavian, David G. Hasko, Hashem Zare-Hoseini
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 67:2883-2896
A capacitive DAC is an important building block of a charge-redistribution SAR ADC, for its size has a significant impact on performance. For medium- to high-resolution applications, the size of the DAC is typically determined by random mismatches. A
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 67:1789-1802
Dickson charge-pump (CP) is proposed here to realize a voltage-to-time converter (VTC) within an array of time-domain comparators of a 54-level time-mode subthreshold flash ADC operating at 0.36V. Two identical CPs in each of the 54 ADC slices conver
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 67:578-589
In this paper, we introduce a new switched-capacitor (SC) passive delta-sigma ( $\Delta \Sigma $ ) modulator architecture. It is based on a charge-sharing rotation technique, which eliminates any inter-stage loading effects that plague the convention
An Adaptive-Resolution Quasi-Level-Crossing-Sampling ADC Based on Residue Quantization in 28-nm CMOS
Publikováno v:
IEEE Solid-State Circuits Letters
We present a digitally intensive adaptive-resolution (AR) quasi-level-crossing-sampling (quasi-LCS) analog-to-digital converter (ADC) for Internet-of-Things wireless networks, where the power consumed in data transmission, processing, and storage can